s3c44b0x.h

按键+LED驱动实验 基于TEB-44B0实验平台 包括按键+LED驱动程序与测按键试程序

#ifndef _S3C44B0X_H_
#define _S3C44B0X_H_

/**
 * register definitions for SAMSUNG S3C44B0X
 *
 * Copyright (C) 2003 Christian Schulte <[e-mail]>
 *
 */
 
/*******************/
/*** CPU WRAPPER ***/
/*******************/

#define S3C44B0X_SYSCFG			0x01c00000
#define S3C44B0X_NCACHBE0		0x01c00004 /* configuration of non-cachable areas */
#define S3C44B0X_NCACHBE1		0x01c00008 /* configuration of non-cachable areas */
#define S3C44B0X_SBUSCON		0x01c40000 /* bus configuration */

/* SYSCFG */
#define S3C44B0X_SYSCFG_DA		0x00000020 /* Data Abort disable */
#define S3C44B0X_SYSCFG_RSE		0x00000010 /* Read Stall Option enable */
#define S3C44B0X_SYSCFG_WE		0x00000008 /* Write Buffer enable */

#define S3C44B0X_SYSCFG_CM_NONE		0x00000000 /* Cache Mode */
#define S3C44B0X_SYSCFG_CM_4K		0x00000002
#define S3C44B0X_SYSCFG_CM_8K		0x00000006

#define S3C44B0X_SYSCFG_SE		0x00000001 /* Stall Option enable */

/* SBUSCON */
#define S3C44B0X_SBUSCON_FIX		0x80000000 /* use the fixed configuration that follows (instead of round-robin) */
#define S3C44B0X_SBUSCON_S_LCD_DMA_1	0x00000000 /* read the bus priority of LCD-DMA */
#define S3C44B0X_SBUSCON_S_LCD_DMA_2	0x00004000
#define S3C44B0X_SBUSCON_S_LCD_DMA_3	0x00008000
#define S3C44B0X_SBUSCON_S_LCD_DMA_4	0x0000c000
#define S3C44B0X_SBUSCON_S_ZDMA_1	0x00000000 /* read the bus priority of Z DMA */
#define S3C44B0X_SBUSCON_S_ZDMA_2	0x00001000
#define S3C44B0X_SBUSCON_S_ZDMA_3	0x00002000
#define S3C44B0X_SBUSCON_S_ZDMA_4	0x00003000
#define S3C44B0X_SBUSCON_S_BDMA_1	0x00000000 /* read the bus priority of B DMA */
#define S3C44B0X_SBUSCON_S_BDMA_2	0x00000400
#define S3C44B0X_SBUSCON_S_BDMA_3	0x00000800
#define S3C44B0X_SBUSCON_S_BDMA_4	0x00000c00
#define S3C44B0X_SBUSCON_S_BREQ_1	0x00000000 /* read the bus priority of external BREAK REQUEST */
#define S3C44B0X_SBUSCON_S_BREQ_2	0x00000100
#define S3C44B0X_SBUSCON_S_BREQ_3	0x00000200
#define S3C44B0X_SBUSCON_S_BREQ_4	0x00000300

#define S3C44B0X_SBUSCON_LCD_DMA_1	0x00000000 /* set the bus priority of LCD-DMA */
#define S3C44B0X_SBUSCON_LCD_DMA_2	0x00000040
#define S3C44B0X_SBUSCON_LCD_DMA_3	0x00000080
#define S3C44B0X_SBUSCON_LCD_DMA_4	0x000000c0
#define S3C44B0X_SBUSCON_ZDMA_1		0x00000000 /* set the bus priority of Z DMA */
#define S3C44B0X_SBUSCON_ZDMA_2		0x00000010
#define S3C44B0X_SBUSCON_ZDMA_3		0x00000020
#define S3C44B0X_SBUSCON_ZDMA_4		0x00000030
#define S3C44B0X_SBUSCON_BDMA_1		0x00000000 /* set the bus priority of B DMA */
#define S3C44B0X_SBUSCON_BDMA_2		0x00000004
#define S3C44B0X_SBUSCON_BDMA_3		0x00000008
#define S3C44B0X_SBUSCON_BDMA_4		0x0000000c
#define S3C44B0X_SBUSCON_BREQ_1		0x00000000 /* set the bus priority of external BREAK REQUEST */
#define S3C44B0X_SBUSCON_BREQ_2		0x00000001
#define S3C44B0X_SBUSCON_BREQ_3		0x00000002
#define S3C44B0X_SBUSCON_BREQ_4		0x00000003

  /*************************/
  /*** MEMORY CONTROLLER ***/
  /*************************/

#define S3C44B0X_BWSCON			0x01c80000 /* Bank size, width燼nd type of memory */
#define S3C44B0X_BANKCON0		0x01c80004 /* timing and page modes */
#define S3C44B0X_BANKCON1		0x01c80008
#define S3C44B0X_BANKCON2		0x01c8000c
#define S3C44B0X_BANKCON3		0x01c80010
#define S3C44B0X_BANKCON4		0x01c80014
#define S3C44B0X_BANKCON5		0x01c80018
#define S3C44B0X_BANKCON6		0x01c8001c
#define S3C44B0X_BANKCON7		0x01c80020
#define S3C44B0X_REFRESH		0x01c80024 /* refresh timing */
#define S3C44B0X_BANKSIZE		0x01c80028 /* bank sizes 2,4,8,16,32 MB */
#define S3C44B0X_MRSRB6			0x01c8002c /* burst settings, CAS latency */
#define S3C44B0X_MRSRB7			0x01c80030

/* BWSCON */
#define S3C44B0X_BWSCON_ST7		0x80000000 /* use UB/LB addressing */
#define S3C44B0X_BWSCON_WS7		0x40000000 /* waitstate enable */
#define S3C44B0X_BWSCON_DW7_8		0x00000000 /* data bus width 8bit */
#define S3C44B0X_BWSCON_DW7_16		0x10000000 /* data bus width 16bit */
#define S3C44B0X_BWSCON_DW7_32		0x20000000 /* data bus width 32bit */

#define S3C44B0X_BWSCON_ST6		0x08000000 /* use UB/LB addressing */
#define S3C44B0X_BWSCON_WS6		0x04000000 /* waitstate enable */
#define S3C44B0X_BWSCON_DW6_8		0x00000000 /* data bus width 8bit */
#define S3C44B0X_BWSCON_DW6_16		0x01000000 /* data bus width 16bit */
#define S3C44B0X_BWSCON_DW6_32		0x02000000 /* data bus width 32bit */

#define S3C44B0X_BWSCON_ST5		0x00800000 /* use UB/LB addressing */
#define S3C44B0X_BWSCON_WS5		0x00400000 /* waitstate enable */
#define S3C44B0X_BWSCON_DW5_8		0x00000000 /* data bus width 8bit */
#define S3C44B0X_BWSCON_DW5_16		0x00100000 /* data bus width 16bit */
#define S3C44B0X_BWSCON_DW5_32		0x00200000 /* data bus width 32bit */

#define S3C44B0X_BWSCON_ST4		0x00080000 /* use UB/LB addressing */
#define S3C44B0X_BWSCON_WS4		0x00040000 /* waitstate enable */
#define S3C44B0X_BWSCON_DW4_8		0x00000000 /* data bus width 8bit */
#define S3C44B0X_BWSCON_DW4_16		0x00010000 /* data bus width 16bit */
#define S3C44B0X_BWSCON_DW4_32		0x00020000 /* data bus width 32bit */

#define S3C44B0X_BWSCON_ST3		0x00008000 /* use UB/LB addressing */
#define S3C44B0X_BWSCON_WS3		0x00004000 /* waitstate enable */
#define S3C44B0X_BWSCON_DW3_8		0x00000000 /* data bus width 8bit */
#define S3C44B0X_BWSCON_DW3_16		0x00001000 /* data bus width 16bit */
#define S3C44B0X_BWSCON_DW3_32		0x00002000 /* data bus width 32bit */

#define S3C44B0X_BWSCON_ST2		0x00000800 /* use UB/LB addressing */
#define S3C44B0X_BWSCON_WS2		0x00000400 /* waitstate enable */
#define S3C44B0X_BWSCON_DW2_8		0x00000000 /* data bus width 8bit */
#define S3C44B0X_BWSCON_DW2_16		0x00000100 /* data bus width 16bit */
#define S3C44B0X_BWSCON_DW2_32		0x00000200 /* data bus width 32bit */

#define S3C44B0X_BWSCON_ST1		0x00000080 /* use UB/LB addressing */
#define S3C44B0X_BWSCON_WS1		0x00000040 /* waitstate enable */
#define S3C44B0X_BWSCON_DW1_8		0x00000000 /* data bus width 8bit */
#define S3C44B0X_BWSCON_DW1_16		0x00000010 /* data bus width 16bit */
#define S3C44B0X_BWSCON_DW1_32		0x00000020 /* data bus width 32bit */

#define S3C44B0X_BWSCON_DW0_8		0x00000000 /* data bus width 8bit */
#define S3C44B0X_BWSCON_DW0_16		0x00000002 /* data bus width 16bit */
#define S3C44B0X_BWSCON_DW0_32		0x00000004 /* data bus width 32bit */

#define S3C44B0X_BWSCON_ENDIAN_BIG	0x00000001 /* read-only, samples the endianess input pin */

/* BANKCON */
#define S3C44B0X_BANKCON_TACS_0		0x00000000 /* time, adress setup to CS (in clocks) */
#define S3C44B0X_BANKCON_TACS_1		0x00002000
#define S3C44B0X_BANKCON_TACS_2		0x00004000
#define S3C44B0X_BANKCON_TACS_4		0x00006000

#define S3C44B0X_BANKCON_TCOS_0		0x00000000 /* time, CS to nOE (in clocks) */
#define S3C44B0X_BANKCON_TCOS_1		0x00000800
#define S3C44B0X_BANKCON_TCOS_2		0x00001000
#define S3C44B0X_BANKCON_TCOS_4		0x00001800

#define S3C44B0X_BANKCON_TACC_1		0x00000000 /* access cycle in clocks (in clocks) */
#define S3C44B0X_BANKCON_TACC_2		0x00000100
#define S3C44B0X_BANKCON_TACC_3		0x00000200
#define S3C44B0X_BANKCON_TACC_4		0x00000300
#define S3C44B0X_BANKCON_TACC_6		0x00000400
#define S3C44B0X_BANKCON_TACC_8		0x00000500
#define S3C44B0X_BANKCON_TACC_10	0x00000600
#define S3C44B0X_BANKCON_TACC_14	0x00000700

#define S3C44B0X_BANKCON_TOCH_0		0x00000000 /* time, CS hold on nOE (in clocks) */
#define S3C44B0X_BANKCON_TOCH_1		0x00000040
#define S3C44B0X_BANKCON_TOCH_2		0x00000080
#define S3C44B0X_BANKCON_TOCH_4		0x000000c0

#define S3C44B0X_BANKCON_TCAH_0		0x00000000 /* address hold on after CS (in clocks) */
#define S3C44B0X_BANKCON_TCAH_1		0x00000010
#define S3C44B0X_BANKCON_TCAH_2		0x00000020
#define S3C44B0X_BANKCON_TCAH_4		0x00000030

#define S3C44B0X_BANKCON_TPAC_2		0x00000000 /* page mode access cycle (in clocks) */
#define S3C44B0X_BANKCON_TPAC_3		0x00000004
#define S3C44B0X_BANKCON_TPAC_4		0x00000008
#define S3C44B0X_BANKCON_TPAC_6		0x0000000c

#define S3C44B0X_BANKCON_PMC_1		0x00000000 /* page mode config (in datawords) */
#define S3C44B0X_BANKCON_PMC_4		0x00000001
#define S3C44B0X_BANKCON_PMC_8		0x00000002
#define S3C44B0X_BANKCON_PMC_16		0x00000003

#define S3C44B0X_BANKCON_MT_SRAM	0x00000000 /* memory type selection */
#define S3C44B0X_BANKCON_MT_DRAM	0x00004000
#define S3C44B0X_BANKCON_MT_EDO		0x00008000
#define S3C44B0X_BANKCON_MT_SDRAM	0x00018000

/* only for FP-DRAM or EDO-DRAM */
#define S3C44B0X_BANKCON_TRCD_1		0x00000000 /* RAS to CAS delay */
#define S3C44B0X_BANKCON_TRCD_2		0x00000010
#define S3C44B0X_BANKCON_TRCD_3		0x00000020
#define S3C44B0X_BANKCON_TRCD_4		0x00000030

#define S3C44B0X_BANKCON_TCAS_1		0x00000000 /* CAS pulse width (in clocks) */
#define S3C44B0X_BANKCON_TCAS_2		0x00000008

#define S3C44B0X_BANKCON_TCP_1		0x00000000 /* CAS precharge (in clocks) */
#define S3C44B0X_BANKCON_TCP_2		0x00000004

#define S3C44B0X_BANKCON_CAN_8		0x00000000 /* column address number (in bits) */
#define S3C44B0X_BANKCON_CAN_9		0x00000001
#define S3C44B0X_BANKCON_CAN_10		0x00000002
#define S3C44B0X_BANKCON_CAN_11		0x00000003

/* only for SDRAM */
#define S3C44B0X_BANKCON_SDRAM_TRCD_2	0x00000000 /* RAS to CAS delay */
#define S3C44B0X_BANKCON_SDRAM_TRCD_3	0x00000004
#define S3C44B0X_BANKCON_SDRAM_TRCD_4	0x00000008

#define S3C44B0X_BANKCON_SCAN_8		0x00000000 /* column address number (in bits) */
#define S3C44B0X_BANKCON_SCAN_9		0x00000001
#define S3C44B0X_BANKCON_SCAN_10	0x00000002


/* REFRESH */
#define S3C44B0X_REFRESH_REFEN		0x00800000
#define S3C44B0X_REFRESH_TREFMD		0x00400000


#define S3C44B0X_REFRESH_TRP_1_5	0x00000000 /* for DRAM */
#define S3C44B0X_REFRESH_TRP_2_5	0x00000000
#define S3C44B0X_REFRESH_TRP_3_5	0x00000000
#define S3C44B0X_REFRESH_TRP_4_5	0x00000000
#define S3C44B0X_REFRESH_TRP_2		0x00000000 /* for SDRAM */
#define S3C44B0X_REFRESH_TRP_3		0x00000000
#define S3C44B0X_REFRESH_TRP_4		0x00000000
#define S3C44B0X_REFRESH_TRP_NONE	0x00000000

#define S3C44B0X_REFRESH_TRC_4		0x00000000 /* SDRAM RC minimum time */
#define S3C44B0X_REFRESH_TRC_5		0x00040000
#define S3C44B0X_REFRESH_TRC_6		0x00080000
#define S3C44B0X_REFRESH_TRC_7		0x000c0000

#define S3C44B0X_REFRESH_TCHR_1		0x00000000 /* CAS Hold Time (DRAM) */
#define S3C44B0X_REFRESH_TCHR_2		0x00010000
#define S3C44B0X_REFRESH_TCHR_3		0x00020000
#define S3C44B0X_REFRESH_TCHR_4		0x00030000

#define S3C44B0X_REFRESH_COUNTER	0x000003FF /* mask for the refresh counter (bit 0-10) */

/* BANKSIZE */
#define S3C44B0X_BANKSIZE_SCLKEN	0x00000010
#define S3C44B0X_BANKSIZE_BK76MAP_2	0x00000004
#define S3C44B0X_BANKSIZE_BK76MAP_4	0x00000005
#define S3C44B0X_BANKSIZE_BK76MAP_8	0x00000006
#define S3C44B0X_BANKSIZE_BK76MAP_16	0x00000007
#define S3C44B0X_BANKSIZE_BK76MAP_32	0x00000000

/* MRSRB */
#define S3C44B0X_MRSRB_WBL		0x00000200
#define S3C44B0X_MRSRB_CL_1		0x00000000
#define S3C44B0X_MRSRB_CL_2		0x00000020
#define S3C44B0X_MRSRB_CL_3		0x00000030
#define S3C44B0X_MRSRB_BT_SEQ		0x00000000
#define S3C44B0X_MRSRB_BT_NONSEQ	0x00000008
#define S3C44B0X_MRSRB_BL_1		0x00000000

  /************/
  /*** UART ***/
  /************/
  
#define S3C44B0X_ULCON0			0x01d00000
#define S3C44B0X_UCON0			0x01d00004
#define S3C44B0X_UFCON0			0x01d00008
#define S3C44B0X_UMCON0			0x01d0000c
#define S3C44B0X_UTRSTAT0		0x01d00010
#define S3C44B0X_UERSTAT0		0x01d00014
#define S3C44B0X_UFSTAT0		0x01d00018
#define S3C44B0X_UMSTAT0		0x01d0001c

#ifdef CONFIG_CPU_BIG_ENDIAN
#define S3C44B0X_UTXH0			0x01d00023
#define S3C44B0X_URXH0			0x01d00027
#else
#define S3C44B0X_UTXH0			0x01d00020
#define S3C44B0X_URXH0			0x01d00024
#endif

#define S3C44B0X_UBRDIV0		0x01d00028

#define S3C44B0X_ULCON1			0x01d04000
#define S3C44B0X_UCON1			0x01d04004
#define S3C44B0X_UFCON1			0x01d04008
#define S3C44B0X_UMCON1			0x01d0400c
#define S3C44B0X_UTRSTAT1		0x01d04010
#define S3C44B0X_UERSTAT1		0x01d04014
#define S3C44B0X_UFSTAT1		0x01d04018
#define S3C44B0X_UMSTAT1		0x01d0401c

#ifdef CONFIG_CPU_BIG_ENDIAN
#define S3C44B0X_UTXH1			0x01d04023
#define S3C44B0X_URXH1			0x01d04027
#else
#define S3C44B0X_UTXH1			0x01d04020
#define S3C44B0X_URXH1			0x01d04024
#endif

#define S3C44B0X_UBRDIV1		0x01d04028

/* ULCON */
#define S3C44B0X_ULCON_IR		0x00000040

#define S3C44B0X_ULCON_PAR_NO		0x00000000
#define S3C44B0X_ULCON_PAR_ODD		0x00000020
#define S3C44B0X_ULCON_PAR_EVEN		0x00000028
#define S3C44B0X_ULCON_PAR_1		0x00000030
#define S3C44B0X_ULCON_PAR_0		0x00000038

#define S3C44B0X_ULCON_STOPB_1		0x00000000
#define S3C44B0X_ULCON_STOPB_2		0x00000004

#define S3C44B0X_ULCON_WORDLN_5		0x00000000
#define S3C44B0X_ULCON_WORDLN_6		0x00000001
#define S3C44B0X_ULCON_WORDLN_7		0x00000002
#define S3C44B0X_ULCON_WORDLN_8		0x00000003

/* UCON */
#define S3C44B0X_UCON_TXINT_LEVEL	0x00000200
#define S3C44B0X_UCON_RXINT_LEVEL	0x00000100
#define S3C44B0X_UCON_TXINT_PULSE	0x00000000
#define S3C44B0X_UCON_RXINT_PULSE	0x00000000
#define S3C44B0X_UCON_RX_TIMEOUT_EN	0x00000080
#define S3C44B0X_UCON_RX_ERR_INT_EN	0x00000040
#define S3C44B0X_UCON_LOOP		0x00000020
#define S3C44B0X_UCON_SEND_BREAK	0x00000010

#define S3C44B0X_UCON_TX_DIS		0x00000000
#define S3C44B0X_UCON_TX_MODE_INT_POLL	0x00000004
#define S3C44B0X_UCON_TX_MODE_BDMA0	0x00000008
#define S3C44B0X_UCON_TX_MODE_BDMA1	0x0000000c

#define S3C44B0X_UCON_RX_DIS		0x00000000
#define S3C44B0X_UCON_RX_MODE_INT_POLL	0x00000001
#define S3C44B0X_UCON_RX_MODE_BDMA0	0x00000002
#define S3C44B0X_UCON_RX_MODE_BDMA1	0x00000003

/* UFCON */
#define S3C44B0X_UFCON_TX_FIFO_0	0x00000000 /* TX FIFO byte size */
#define S3C44B0X_UFCON_TX_FIFO_4	0x00000040
#define S3C44B0X_UFCON_TX_FIFO_8	0x00000080
#define S3C44B0X_UFCON_TX_FIFO_12	0x000000c0

#define S3C44B0X_UFCON_RX_FIFO_4	0x00000000 /* RX FIFO byte size */
#define S3C44B0X_UFCON_RX_FIFO_8	0x00000010
#define S3C44B0X_UFCON_RX_FIFO_12	0x00000020
#define S3C44B0X_UFCON_RX_FIFO_16	0x00000030

#define S3C44B0X_UFCON_TX_FIFO_RST	0x00000004
#define S3C44B0X_UFCON_RX_FIFO_RST	0x00000002
#define S3C44B0X_UFCON_FIFO_EN		0x00000001 /* global FIFO enable */