📄 s1eig.mdl
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SrcPort 1
DstBlock "T"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "VIPQ"
Position [450, 71, 490, 164]
ShowPortLabels off
System {
Name "VIPQ"
Location [351, 304, 1039, 737]
Open off
ScreenColor white
Block {
BlockType Inport
Name "vqt"
Position [45, 160, 65, 180]
Port "1"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "iq"
Position [45, 205, 65, 225]
Port "2"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "vdt"
Position [45, 245, 65, 265]
Port "3"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "id"
Position [45, 290, 65, 310]
Port "4"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Fcn
Name "Fcn"
Position [230, 247, 385, 273]
Expr "u[1]*u[2] + u[3]*u[4]"
}
Block {
BlockType Fcn
Name "Fcn1"
Position [230, 297, 385, 323]
Expr "u[1]*u[4] - u[2]*u[3]"
}
Block {
BlockType Fcn
Name "Fcn2"
Position [230, 200, 390, 230]
Expr "sqrt(u[2]*u[2] + u[4]*u[4])"
}
Block {
BlockType Fcn
Name "Fcn3"
Position [230, 151, 390, 179]
Expr "sqrt(u[1]*u[1] + u[3]*u[3])"
}
Block {
BlockType Mux
Name "Mux"
Position [135, 172, 160, 298]
Inputs "4"
}
Block {
BlockType Outport
Name "out_|Vt|"
Position [450, 155, 470, 175]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_|I|"
Position [450, 205, 470, 225]
Port "2"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_P"
Position [450, 250, 470, 270]
Port "3"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_Q"
Position [450, 300, 470, 320]
Port "4"
OutputWhenDisabled held
InitialOutput "0"
}
Line {
SrcBlock "vqt"
SrcPort 1
Points [25, 0; 0, 20]
DstBlock "Mux"
DstPort 1
}
Line {
SrcBlock "iq"
SrcPort 1
Points [25, 0; 0, 5]
DstBlock "Mux"
DstPort 2
}
Line {
SrcBlock "vdt"
SrcPort 1
Points [25, 0; 0, -5]
DstBlock "Mux"
DstPort 3
}
Line {
SrcBlock "id"
SrcPort 1
Points [25, 0; 0, -20]
DstBlock "Mux"
DstPort 4
}
Line {
SrcBlock "Fcn"
SrcPort 1
DstBlock "out_P"
DstPort 1
}
Line {
SrcBlock "Fcn1"
SrcPort 1
DstBlock "out_Q"
DstPort 1
}
Line {
SrcBlock "Mux"
SrcPort 1
Points [0, 0]
Branch {
Points [25, 0; 0, 25]
DstBlock "Fcn"
DstPort 1
}
Branch {
Points [25, 0; 0, 75]
DstBlock "Fcn1"
DstPort 1
}
Branch {
Points [25, 0; 0, -70]
DstBlock "Fcn3"
DstPort 1
}
Branch {
Points [25, 0; 0, -20]
DstBlock "Fcn2"
DstPort 1
}
}
Line {
SrcBlock "Fcn3"
SrcPort 1
DstBlock "out_|Vt|"
DstPort 1
}
Line {
SrcBlock "Fcn2"
SrcPort 1
DstBlock "out_|I|"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "qde2qdr"
Position [135, 210, 175, 270]
ShowPortLabels off
System {
Name "qde2qdr"
Location [277, 287, 802, 474]
Open off
ScreenColor white
Block {
BlockType Inport
Name "vqe"
Position [15, 35, 35, 55]
Port "1"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "vde"
Position [15, 80, 35, 100]
Port "2"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "delta "
Position [15, 124, 35, 146]
Port "3"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Mux
Name "Mux"
Position [75, 50, 105, 130]
ShowName off
Inputs "3"
}
Block {
BlockType Fcn
Name "fcn"
Position [150, 52, 390, 78]
Expr "u[1]*cos(u[3]) - u[2]*sin(u[3])"
}
Block {
BlockType Fcn
Name "fcn1"
Position [150, 97, 390, 123]
Expr "u[1]*sin(u[3]) + u[2]*cos(u[3])"
}
Block {
BlockType Outport
Name "vqr"
Position [445, 55, 465, 75]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "vdr"
Position [445, 100, 465, 120]
Port "2"
OutputWhenDisabled held
InitialOutput "0"
}
Line {
SrcBlock "fcn1"
SrcPort 1
DstBlock "vdr"
DstPort 1
}
Line {
SrcBlock "vqe"
SrcPort 1
Points [10, 0; 0, 20]
DstBlock "Mux"
DstPort 1
}
Line {
SrcBlock "fcn"
SrcPort 1
DstBlock "vqr"
DstPort 1
}
Line {
SrcBlock "Mux"
SrcPort 1
Points [0, 0]
Branch {
Points [15, 0; 0, -25]
DstBlock "fcn"
DstPort 1
}
Branch {
Points [15, 0; 0, 20]
DstBlock "fcn1"
DstPort 1
}
}
Line {
SrcBlock "delta "
SrcPort 1
Points [10, 0; 0, -20]
DstBlock "Mux"
DstPort 3
}
Line {
SrcBlock "vde"
SrcPort 1
DstBlock "Mux"
DstPort 2
}
}
}
Block {
BlockType SubSystem
Name "stator_wdg"
Position [270, 153, 310, 267]
ShowPortLabels off
System {
Name "stator_wdg"
Location [171, 185, 1084, 470]
Open off
ScreenColor white
Block {
BlockType Inport
Name "Eqp"
Position [25, 90, 45, 110]
Port "1"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "Edp"
Position [25, 130, 45, 150]
Port "2"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "vqir"
Position [25, 168, 45, 192]
Port "3"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "vdir"
Position [25, 210, 45, 230]
Port "4"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Fcn
Name "Fcn"
Position [135, 110, 395, 140]
Expr "-((rs+re)*(u[3]-u[1]) - (xpd+xe)*(u[4]-u"
"[2]))/Dz"
}
Block {
BlockType Fcn
Name "Fcn1"
Position [135, 180, 395, 210]
Expr "-((xq+xe)*(u[3]-u[1]) + (rs+re)*(u[4]-u["
"2]))/Dz"
}
Block {
BlockType Fcn
Name "Fcn2"
Position [540, 85, 670, 115]
Expr "u[1] -rs*u[3]- xpd*u[4] "
}
Block {
BlockType Fcn
Name "Fcn3"
Position [540, 156, 680, 184]
Expr "u[2] + xq*u[3] - rs*u[4]"
}
Block {
BlockType Mux
Name "Mux"
Position [85, 84, 110, 236]
Inputs "4"
}
Block {
BlockType Mux
Name "Mux1"
Position [485, 74, 505, 196]
Inputs "4"
}
Block {
BlockType Outport
Name "out_vqt"
Position [700, 90, 720, 110]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_vdt"
Position [705, 160, 725, 180]
Port "2"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_iq"
Position [425, 115, 445, 135]
Port "3"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_id"
Position [430, 185, 450, 205]
Port "4"
OutputWhenDisabled held
InitialOutput "0"
}
Line {
SrcBlock "Mux"
SrcPort 1
Points [0, 0]
Branch {
Points [0, -35]
DstBlock "Fcn"
DstPort 1
}
Branch {
Points [0, 35]
DstBlock "Fcn1"
DstPort 1
}
}
Line {
SrcBlock "Mux1"
SrcPort 1
Points [0, 0]
Branch {
Points [5, 0; 0, -35]
DstBlock "Fcn2"
DstPort 1
}
Branch {
Points [5, 0; 0, 35]
DstBlock "Fcn3"
DstPort 1
}
}
Line {
SrcBlock "Fcn2"
SrcPort 1
DstBlock "out_vqt"
DstPort 1
}
Line {
SrcBlock "Fcn3"
SrcPort 1
DstBlock "out_vdt"
DstPort 1
}
Line {
SrcBlock "vqir"
SrcPort 1
DstBlock "Mux"
DstPort 3
}
Line {
SrcBlock "vdir"
SrcPort 1
DstBlock "Mux"
DstPort 4
}
Line {
SrcBlock "Fcn1"
SrcPort 1
Points [0, 0]
Branch {
DstBlock "out_id"
DstPort 1
}
Branch {
Points [10, 0; 0, -15]
DstBlock "Mux1"
DstPort 4
}
}
Line {
SrcBlock "Fcn"
SrcPort 1
Points [0, 0]
Branch {
DstBlock "out_iq"
DstPort 1
}
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