s3.mdl

simulink electrical machine(2)

	      LimitOutput	      off
	      UpperSaturationLimit      "inf"
	      LowerSaturationLimit      "-inf"
	      ShowSaturationPort      off
	      ShowStatePort	      off
	      AbsoluteTolerance	      "auto"
	    }
	    Block {
	      BlockType		      Integrator
	      Name		      "psiq_"
	      Position		      [350, 127, 380, 153]
	      ExternalReset	      none
	      InitialConditionSource      internal
	      InitialCondition	      "Psiqo"
	      LimitOutput	      off
	      UpperSaturationLimit      "inf"
	      LowerSaturationLimit      "-inf"
	      ShowSaturationPort      off
	      ShowStatePort	      off
	      AbsoluteTolerance	      "auto"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out_psiq"
	      Position		      [585, 45, 605, 65]
	      Port		      "1"
	      OutputWhenDisabled      held
	      InitialOutput	      "0"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out_-iq"
	      Position		      [665, 205, 685, 225]
	      Port		      "2"
	      OutputWhenDisabled      held
	      InitialOutput	      "0"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out_psimq"
	      Position		      [665, 120, 685, 140]
	      Port		      "3"
	      OutputWhenDisabled      held
	      InitialOutput	      "0"
	    }
	    Line {
	      SrcBlock		      "In_wrpsid"
	      SrcPort		      1
	      Points		      [20, 0; 0, -20]
	      DstBlock		      "Mux"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "In_vqr"
	      SrcPort		      1
	      Points		      [20, 0; 0, 10]
	      DstBlock		      "Mux"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Mux"
	      SrcPort		      1
	      DstBlock		      "Fcn"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Fcn"
	      SrcPort		      1
	      DstBlock		      "psiq_"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Mux2"
	      SrcPort		      1
	      DstBlock		      "Fcn2"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Fcn2"
	      SrcPort		      1
	      DstBlock		      "psipkq_"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "psiq_"
	      SrcPort		      1
	      Points		      [29, 0]
	      Branch {
		Points			[-24, 0; 0, 65; -275, 0; 0, -30]
		DstBlock		"Mux"
		DstPort			4
	      }
	      Branch {
		Points			[-24, 0; 0, -30]
		DstBlock		"Mux3"
		DstPort			1
	      }
	      Branch {
		Points			[1, 0; 0, 55]
		DstBlock		"Mux4"
		DstPort			1
	      }
	      Branch {
		Points			[-24, 0; 0, -85]
		DstBlock		"Out_psiq"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "psipkq_"
	      SrcPort		      1
	      Points		      [24, 0]
	      Branch {
		Points			[1, 0; 0, 60; -290, 0; 0, -45]
		DstBlock		"Mux2"
		DstPort			2
	      }
	      Branch {
		Points			[1, 0; 0, -100]
		DstBlock		"Mux3"
		DstPort			2
	      }
	    }
	    Line {
	      SrcBlock		      "Mux3"
	      SrcPort		      1
	      DstBlock		      "Fcn3"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Mux4"
	      SrcPort		      1
	      DstBlock		      "Fcn4"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Fcn3"
	      SrcPort		      1
	      Points		      [15, 0]
	      Branch {
		Points			[0, 185; -220, 0; 0, -85]
		DstBlock		"Mux4"
		DstPort			2
	      }
	      Branch {
		Points			[0, 185; -550, 0; 0, -85]
		DstBlock		"Mux2"
		DstPort			1
	      }
	      Branch {
		Points			[0, -50; -525, 0; 0, 20]
		DstBlock		"Mux"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Out_psimq"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Fcn4"
	      SrcPort		      1
	      DstBlock		      "Out_-iq"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  Outport
	  Name			  "out_Pgen"
	  Position		  [720, 105, 740, 125]
	  Port			  "1"
	  OutputWhenDisabled	  held
	  InitialOutput		  "0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "out_Qgen"
	  Position		  [680, 120, 700, 140]
	  Port			  "2"
	  OutputWhenDisabled	  held
	  InitialOutput		  "0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "out_delta"
	  Position		  [720, 220, 740, 240]
	  Port			  "3"
	  OutputWhenDisabled	  held
	  InitialOutput		  "0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "out_Tem"
	  Position		  [720, 290, 740, 310]
	  Port			  "4"
	  OutputWhenDisabled	  held
	  InitialOutput		  "0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "out_(wr-we)/wb"
	  Position		  [720, 325, 740, 345]
	  Port			  "5"
	  OutputWhenDisabled	  held
	  InitialOutput		  "0"
	}
	Line {
	  SrcBlock		  "Rotor"
	  SrcPort		  2
	  Points		  [0, 0]
	  Branch {
	    Points		    [15, 0; 0, -85]
	    DstBlock		    "prod1"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [15, 0; 0, 115]
	    DstBlock		    "prod2"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "q_cct"
	  SrcPort		  1
	  Points		  [0, 0]
	  Branch {
	    Points		    [5, 0; 0, 150]
	    DstBlock		    "prod2"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [85, 0; 0, 65]
	    DstBlock		    "Rotor"
	    DstPort		    3
	  }
	}
	Line {
	  SrcBlock		  "d_cct"
	  SrcPort		  1
	  Points		  [0, 0]
	  Branch {
	    Points		    [45, 0; 0, -125]
	    DstBlock		    "prod1"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [100, 0; 0, -35]
	    DstBlock		    "Rotor"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "prod2"
	  SrcPort		  1
	  Points		  [-35, 0; 0, -60]
	  DstBlock		  "d_cct"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Rotor"
	  SrcPort		  3
	  DstBlock		  "out_Tem"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "in_Ex"
	  SrcPort		  1
	  DstBlock		  "d_cct"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "Rotor"
	  SrcPort		  4
	  DstBlock		  "out_(wr-we)/wb"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "in_Tmech"
	  SrcPort		  1
	  DstBlock		  "Rotor"
	  DstPort		  5
	}
	Line {
	  SrcBlock		  "in_vqse"
	  SrcPort		  1
	  DstBlock		  "Mux1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "in_vdse"
	  SrcPort		  1
	  DstBlock		  "Mux1"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "Rotor"
	  SrcPort		  1
	  Points		  [0, 0]
	  Branch {
	    DstBlock		    "out_delta"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [5, 0; 0, -75; -540, 0; 0, 65]
	    DstBlock		    "Mux1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Mux1"
	  SrcPort		  1
	  Points		  [0, 0]
	  Branch {
	    Points		    [5, 0; 0, -15]
	    DstBlock		    "Fcn"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [5, 0; 0, 35]
	    DstBlock		    "Fcn1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "q_cct"
	  SrcPort		  2
	  Points		  [0, 0]
	  Branch {
	    DstBlock		    "Rotor"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [55, 0; 0, -130]
	    DstBlock		    "VIPQ"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "d_cct"
	  SrcPort		  2
	  Points		  [0, 0]
	  Branch {
	    DstBlock		    "Rotor"
	    DstPort		    4
	  }
	  Branch {
	    Points		    [70, 0; 0, -175]
	    DstBlock		    "VIPQ"
	    DstPort		    4
	  }
	}
	Line {
	  SrcBlock		  "Fcn"
	  SrcPort		  1
	  Points		  [0, 0]
	  Branch {
	    Points		    [25, 0; 0, -25]
	    DstBlock		    "q_cct"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [10, 0; 0, -160]
	    DstBlock		    "VIPQ"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Fcn1"
	  SrcPort		  1
	  Points		  [0, 0]
	  Branch {
	    DstBlock		    "d_cct"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [25, 0; 0, -180]
	    DstBlock		    "VIPQ"
	    DstPort		    3
	  }
	}
	Line {
	  SrcBlock		  "VIPQ"
	  SrcPort		  3
	  DstBlock		  "out_Pgen"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "VIPQ"
	  SrcPort		  4
	  DstBlock		  "out_Qgen"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "prod1"
	  SrcPort		  1
	  Points		  [-25, 0; 0, 70]
	  DstBlock		  "q_cct"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "VIPQ"
	  SrcPort		  1
	  DstBlock		  "T"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "q_cct"
	  SrcPort		  3
	  DstBlock		  "T2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "d_cct"
	  SrcPort		  3
	  DstBlock		  "T3"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "d_cct"
	  SrcPort		  4
	  Points		  [0, 10]
	  DstBlock		  "T4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "VIPQ"
	  SrcPort		  2
	  DstBlock		  "T1"
	  DstPort		  1
	}
	Annotation {
	  Position		  [387, 277]
	  VerticalAlignment	  top
	  Text			  "vdr"
	}
	Annotation {
	  Position		  [390, 230]
	  VerticalAlignment	  top
	  Text			  "vqr"
	}
	Annotation {
	  Position		  [482, 219]
	  VerticalAlignment	  top
	  Text			  "-iqr"
	}
	Annotation {
	  Position		  [487, 274]
	  VerticalAlignment	  top
	  Text			  "psid"
	}
	Annotation {
	  Position		  [487, 204]
	  VerticalAlignment	  top
	  Text			  "psiq"
	}
	Annotation {
	  Position		  [487, 289]
	  VerticalAlignment	  top
	  Text			  "-idr"
	}
      }
    }
    Block {
      BlockType		      Outport
      Name		      "Pgen"
      Position		      [335, 70, 355, 90]
      Port		      "1"
      OutputWhenDisabled      held
      InitialOutput	      "0"
    }
    Block {
      BlockType		      Outport
      Name		      "Qgen"
      Position		      [335, 115, 355, 135]
      Port		      "2"
      OutputWhenDisabled      held
      InitialOutput	      "0"
    }
    Block {
      BlockType		      Outport
      Name		      "delta"
      Position		      [335, 160, 355, 180]
      Port		      "3"
      OutputWhenDisabled      held
      InitialOutput	      "0"
    }
    Block {
      BlockType		      Outport
      Name		      "Tem"
      Position		      [335, 205, 355, 225]
      Port		      "4"
      OutputWhenDisabled      held
      InitialOutput	      "0"
    }
    Block {
      BlockType		      Outport
      Name		      "(wr-we)/wb"
      Position		      [335, 250, 355, 270]
      Port		      "5"
      OutputWhenDisabled      held
      InitialOutput	      "0"
    }
    Line {
      SrcBlock		      "Tmech"
      SrcPort		      1
      DstBlock		      "smwes"
      DstPort		      4
    }
    Line {
      SrcBlock		      "smwes"
      SrcPort		      1
      DstBlock		      "Pgen"
      DstPort		      1
    }
    Line {
      SrcBlock		      "smwes"
      SrcPort		      2
      DstBlock		      "Qgen"
      DstPort		      1
    }
    Line {
      SrcBlock		      "smwes"
      SrcPort		      3
      DstBlock		      "delta"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Ex"
      SrcPort		      1
      DstBlock		      "smwes"
      DstPort		      3
    }
    Line {
      SrcBlock		      "vqe"
      SrcPort		      1
      DstBlock		      "smwes"
      DstPort		      1
    }
    Line {
      SrcBlock		      "vde"
      SrcPort		      1
      DstBlock		      "smwes"
      DstPort		      2
    }
    Line {
      SrcBlock		      "smwes"
      SrcPort		      4
      DstBlock		      "Tem"
      DstPort		      1
    }
    Line {
      SrcBlock		      "smwes"
      SrcPort		      5
      DstBlock		      "(wr-we)/wb"
      DstPort		      1
    }
  }
}