📄 s1c.mdl
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Name "Mux2"
Position [450, 286, 470, 339]
Inputs "2"
}
Block {
BlockType Mux
Name "Mux3"
Position [445, 193, 465, 257]
Inputs "2"
}
Block {
BlockType Mux
Name "Mux4"
Position [450, 114, 470, 161]
Inputs "2"
}
Block {
BlockType Integrator
Name "psidr'_"
Position [345, 287, 375, 313]
ExternalReset none
InitialConditionSource internal
InitialCondition "Psipdro"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
}
Block {
BlockType Integrator
Name "psids_"
Position [335, 137, 365, 163]
ExternalReset none
InitialConditionSource internal
InitialCondition "Psidso"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
}
Block {
BlockType Outport
Name "out_psids"
Position [735, 65, 755, 85]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_ids"
Position [735, 130, 755, 150]
Port "2"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_idr'"
Position [735, 305, 755, 325]
Port "3"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_psidr'"
Position [735, 260, 755, 280]
Port "4"
OutputWhenDisabled held
InitialOutput "0"
}
Line {
SrcBlock "Fcn5"
SrcPort 1
DstBlock "out_idr'"
DstPort 1
}
Line {
SrcBlock "in_(wr/wb)*psiqr'"
SrcPort 1
DstBlock "Mux1"
DstPort 2
}
Line {
SrcBlock "in_vds"
SrcPort 1
DstBlock "Mux"
DstPort 2
}
Line {
SrcBlock "Fcn4"
SrcPort 1
DstBlock "out_ids"
DstPort 1
}
Line {
SrcBlock "Mux"
SrcPort 1
DstBlock "Fcn"
DstPort 1
}
Line {
SrcBlock "Fcn"
SrcPort 1
DstBlock "psids_"
DstPort 1
}
Line {
SrcBlock "Fcn2"
SrcPort 1
DstBlock "psidr'_"
DstPort 1
}
Line {
SrcBlock "Mux3"
SrcPort 1
DstBlock "Fcn3"
DstPort 1
}
Line {
SrcBlock "Mux4"
SrcPort 1
DstBlock "Fcn4"
DstPort 1
}
Line {
SrcBlock "psids_"
SrcPort 1
Points [0, 0]
Branch {
Points [35, 0; 0, -75]
DstBlock "out_psids"
DstPort 1
}
Branch {
Points [35, 0; 0, 60]
DstBlock "Mux3"
DstPort 1
}
Branch {
Points [35, 0; 0, -25]
DstBlock "Mux4"
DstPort 1
}
Branch {
Points [35, 0; 0, 60; -325, 0; 0, -30]
DstBlock "Mux"
DstPort 3
}
}
Line {
SrcBlock "Fcn3"
SrcPort 1
Points [0, 0]
Branch {
Points [55, 0; 0, -45; -270, 0; 0, -30]
DstBlock "Mux4"
DstPort 2
}
Branch {
Points [55, 0; 0, 140; -620, 0; 0, -40]
DstBlock "Mux1"
DstPort 3
}
Branch {
Points [55, 0; 0, -135; -615, 0; 0, 30]
DstBlock "Mux"
DstPort 1
}
Branch {
Points [55, 0; 0, 140; -285, 0; 0, -40]
DstBlock "Mux2"
DstPort 2
}
}
Line {
SrcBlock "Mux1"
SrcPort 1
DstBlock "Fcn2"
DstPort 1
}
Line {
SrcBlock "psidr'_"
SrcPort 1
Points [0, 0]
Branch {
Points [35, 0; 0, -30]
DstBlock "out_psidr'"
DstPort 1
}
Branch {
Points [35, 0; 0, -60; -330, 0; 0, 35]
DstBlock "Mux1"
DstPort 1
}
Branch {
Points [35, 0; 0, -60]
DstBlock "Mux3"
DstPort 2
}
Branch {
DstBlock "Mux2"
DstPort 1
}
}
Line {
SrcBlock "Mux2"
SrcPort 1
DstBlock "Fcn5"
DstPort 1
}
Annotation {
Position [392, 283]
VerticalAlignment top
Text "psidr'"
}
Annotation {
Position [602, 299]
VerticalAlignment top
Text "idr'"
}
Annotation {
Position [667, 207]
VerticalAlignment top
Text "psiqm"
}
Annotation {
Position [382, 132]
VerticalAlignment top
Text "psids"
}
Annotation {
Position [602, 127]
VerticalAlignment top
Text "ids"
}
}
}
Block {
BlockType Product
Name "Product"
Position [275, 144, 295, 166]
Orientation left
Inputs "2"
}
Block {
BlockType Product
Name "Product1"
Position [275, 188, 295, 212]
Orientation left
Inputs "2"
}
Block {
BlockType SubSystem
Name "Qaxis"
Position [240, 75, 275, 130]
ShowPortLabels off
System {
Name "Qaxis"
Location [-49, 147, 755, 561]
Open off
ScreenColor white
Block {
BlockType Inport
Name "in_vqs"
Position [50, 140, 70, 160]
Port "1"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "in_(wr/wb)*psidr'"
Position [45, 290, 65, 310]
Port "2"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Fcn
Name "Fcn"
Position [145, 135, 310, 165]
Expr "wb*(u[2]+(rs/xls)*(u[1]-u[3]))"
}
Block {
BlockType Fcn
Name "Fcn2"
Position [145, 284, 325, 316]
Expr "wb*(u[2] +(rpr/xplr)*(u[3]-u[1]))"
}
Block {
BlockType Fcn
Name "Fcn3"
Position [485, 207, 635, 243]
Expr "xM*(u[1]/xls+u[2]/xplr)"
}
Block {
BlockType Fcn
Name "Fcn4"
Position [495, 126, 585, 154]
Expr "(u[1]-u[2])/xls"
}
Block {
BlockType Fcn
Name "Fcn5"
Position [490, 300, 585, 330]
Expr "(u[1]-u[2])/xplr"
}
Block {
BlockType Mux
Name "Mux"
Position [100, 108, 120, 192]
Inputs "3"
}
Block {
BlockType Mux
Name "Mux1"
Position [105, 262, 125, 338]
Inputs "3"
}
Block {
BlockType Mux
Name "Mux2"
Position [450, 286, 470, 339]
Inputs "2"
}
Block {
BlockType Mux
Name "Mux3"
Position [445, 193, 465, 257]
Inputs "2"
}
Block {
BlockType Mux
Name "Mux4"
Position [450, 114, 470, 161]
Inputs "2"
}
Block {
BlockType Integrator
Name "psiqr'_"
Position [345, 287, 375, 313]
ExternalReset none
InitialConditionSource internal
InitialCondition "Psipqro"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
}
Block {
BlockType Integrator
Name "psiqs_"
Position [335, 137, 365, 163]
ExternalReset none
InitialConditionSource internal
InitialCondition "Psiqso"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
}
Block {
BlockType Outport
Name "out_psiqs"
Position [735, 65, 755, 85]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_iqs"
Position [735, 130, 755, 150]
Port "2"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_iqr'"
Position [735, 305, 755, 325]
Port "3"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_psiqr'"
Position [735, 260, 755, 280]
Port "4"
OutputWhenDisabled held
InitialOutput "0"
}
Line {
SrcBlock "Fcn5"
SrcPort 1
DstBlock "out_iqr'"
DstPort 1
}
Line {
SrcBlock "in_(wr/wb)*psidr'"
SrcPort 1
DstBlock "Mux1"
DstPort 2
}
Line {
SrcBlock "in_vqs"
SrcPort 1
DstBlock "Mux"
DstPort 2
}
Line {
SrcBlock "Fcn4"
SrcPort 1
DstBlock "out_iqs"
DstPort 1
}
Line {
SrcBlock "Mux"
SrcPort 1
DstBlock "Fcn"
DstPort 1
}
Line {
SrcBlock "Fcn"
SrcPort 1
DstBlock "psiqs_"
DstPort 1
}
Line {
SrcBlock "Fcn2"
SrcPort 1
DstBlock "psiqr'_"
DstPort 1
}
Line {
SrcBlock "Mux3"
SrcPort 1
DstBlock "Fcn3"
DstPort 1
}
Line {
SrcBlock "Mux4"
SrcPort 1
DstBlock "Fcn4"
DstPort 1
}
Line {
SrcBlock "psiqs_"
SrcPort 1
Points [0, 0]
Branch {
Points [35, 0; 0, -75]
DstBlock "out_psiqs"
DstPort 1
}
Branch {
Points [35, 0; 0, 60]
DstBlock "Mux3"
DstPort 1
}
Branch {
Points [35, 0; 0, -25]
DstBlock "Mux4"
DstPort 1
}
Branch {
Points [35, 0; 0, 60; -325, 0; 0, -30]
DstBlock "Mux"
DstPort 3
}
}
Line {
SrcBlock "Fcn3"
SrcPort 1
Points [0, 0]
Branch {
Points [55, 0; 0, -45; -270, 0; 0, -30]
DstBlock "Mux4"
DstPort 2
}
Branch {
Points [55, 0; 0, 140; -620, 0; 0, -40]
DstBlock "Mux1"
DstPort 3
}
Branch {
Points [55, 0; 0, -135; -615, 0; 0, 30]
DstBlock "Mux"
DstPort 1
}
Branch {
Points [55, 0; 0, 140; -285, 0; 0, -40]
DstBlock "Mux2"
DstPort 2
}
}
Line {
SrcBlock "Mux1"
SrcPort 1
DstBlock "Fcn2"
DstPort 1
}
Line {
SrcBlock "psiqr'_"
SrcPort 1
Points [0, 0]
Branch {
Points [35, 0; 0, -30]
DstBlock "out_psiqr'"
DstPort 1
}
Branch {
Points [35, 0; 0, -60; -330, 0; 0, 35]
DstBlock "Mux1"
DstPort 1
}
Branch {
Points [35, 0; 0, -60]
DstBlock "Mux3"
DstPort 2
}
Branch {
DstBlock "Mux2"
DstPort 1
}
}
Line {
SrcBlock "Mux2"
SrcPort 1
DstBlock "Fcn5"
DstPort 1
}
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