clk.tan.qmsg

一个时钟计数器

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "fen60:u3\|carry " "Info: Detected ripple clock \"fen60:u3\|carry\" as buffer" {  } { { "fen60.vhd" "" { Text "G:/clock/fen60.vhd" 22 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fen60:u3\|carry" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fen60:u2\|carry " "Info: Detected ripple clock \"fen60:u2\|carry\" as buffer" {  } { { "fen60.vhd" "" { Text "G:/clock/fen60.vhd" 22 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fen60:u2\|carry" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkin register fen24:u4\|tem2\[1\] register fen24:u4\|lpm_counter:tem1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 119.05 MHz 8.4 ns Internal " "Info: Clock \"clkin\" has Internal fmax of 119.05 MHz between source register \"fen24:u4\|tem2\[1\]\" and destination register \"fen24:u4\|lpm_counter:tem1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" (period= 8.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.300 ns + Longest register register " "Info: + Longest register to register delay is 7.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fen24:u4\|tem2\[1\] 1 REG LC1_E35 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E35; Fanout = 6; REG Node = 'fen24:u4\|tem2\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fen24:u4|tem2[1] } "NODE_NAME" } } { "fen24.vhd" "" { Text "G:/clock/fen24.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.100 ns) 1.400 ns fen24:u4\|process0~60 2 COMB LC6_E35 1 " "Info: 2: + IC(0.300 ns) + CELL(1.100 ns) = 1.400 ns; Loc. = LC6_E35; Fanout = 1; COMB Node = 'fen24:u4\|process0~60'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { fen24:u4|tem2[1] fen24:u4|process0~60 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 3.000 ns fen24:u4\|process0~57 3 COMB LC7_E35 2 " "Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 3.000 ns; Loc. = LC7_E35; Fanout = 2; COMB Node = 'fen24:u4\|process0~57'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { fen24:u4|process0~60 fen24:u4|process0~57 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.400 ns) 5.300 ns fen24:u4\|tem1~27 4 COMB LC3_E36 7 " "Info: 4: + IC(0.900 ns) + CELL(1.400 ns) = 5.300 ns; Loc. = LC3_E36; Fanout = 7; COMB Node = 'fen24:u4\|tem1~27'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.300 ns" { fen24:u4|process0~57 fen24:u4|tem1~27 } "NODE_NAME" } } { "fen24.vhd" "" { Text "G:/clock/fen24.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.000 ns) 7.300 ns fen24:u4\|lpm_counter:tem1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 5 REG LC7_E34 6 " "Info: 5: + IC(1.000 ns) + CELL(1.000 ns) = 7.300 ns; Loc. = LC7_E34; Fanout = 6; REG Node = 'fen24:u4\|lpm_counter:tem1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.000 ns" { fen24:u4|tem1~27 fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.100 ns ( 69.86 % ) " "Info: Total cell delay = 5.100 ns ( 69.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns ( 30.14 % ) " "Info: Total interconnect delay = 2.200 ns ( 30.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.300 ns" { fen24:u4|tem2[1] fen24:u4|process0~60 fen24:u4|process0~57 fen24:u4|tem1~27 fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.300 ns" { fen24:u4|tem2[1] fen24:u4|process0~60 fen24:u4|process0~57 fen24:u4|tem1~27 fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.300ns 0.000ns 0.900ns 1.000ns } { 0.000ns 1.100ns 1.600ns 1.400ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 9.700 ns + Shortest register " "Info: + Shortest clock path from clock \"clkin\" to destination register is 9.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clkin 1 CLK PIN_126 9 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 9; CLK Node = 'clkin'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "clk.vhd" "" { Text "G:/clock/clk.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns fen60:u2\|carry 2 REG LC1_F34 9 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_F34; Fanout = 9; REG Node = 'fen60:u2\|carry'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { clkin fen60:u2|carry } "NODE_NAME" } } { "fen60.vhd" "" { Text "G:/clock/fen60.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(0.500 ns) 7.400 ns fen60:u3\|carry 3 REG LC2_E6 11 " "Info: 3: + IC(4.000 ns) + CELL(0.500 ns) = 7.400 ns; Loc. = LC2_E6; Fanout = 11; REG Node = 'fen60:u3\|carry'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.500 ns" { fen60:u2|carry fen60:u3|carry } "NODE_NAME" } } { "fen60.vhd" "" { Text "G:/clock/fen60.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(0.000 ns) 9.700 ns fen24:u4\|lpm_counter:tem1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 4 REG LC7_E34 6 " "Info: 4: + IC(2.300 ns) + CELL(0.000 ns) = 9.700 ns; Loc. = LC7_E34; Fanout = 6; REG Node = 'fen24:u4\|lpm_counter:tem1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.300 ns" { fen60:u3|carry fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 30.93 % ) " "Info: Total cell delay = 3.000 ns ( 30.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.700 ns ( 69.07 % ) " "Info: Total interconnect delay = 6.700 ns ( 69.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.700 ns" { clkin fen60:u2|carry fen60:u3|carry fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.700 ns" { clkin clkin~out fen60:u2|carry fen60:u3|carry fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.400ns 4.000ns 2.300ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 9.700 ns - Longest register " "Info: - Longest clock path from clock \"clkin\" to source register is 9.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clkin 1 CLK PIN_126 9 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 9; CLK Node = 'clkin'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "clk.vhd" "" { Text "G:/clock/clk.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns fen60:u2\|carry 2 REG LC1_F34 9 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_F34; Fanout = 9; REG Node = 'fen60:u2\|carry'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { clkin fen60:u2|carry } "NODE_NAME" } } { "fen60.vhd" "" { Text "G:/clock/fen60.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(0.500 ns) 7.400 ns fen60:u3\|carry 3 REG LC2_E6 11 " "Info: 3: + IC(4.000 ns) + CELL(0.500 ns) = 7.400 ns; Loc. = LC2_E6; Fanout = 11; REG Node = 'fen60:u3\|carry'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.500 ns" { fen60:u2|carry fen60:u3|carry } "NODE_NAME" } } { "fen60.vhd" "" { Text "G:/clock/fen60.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(0.000 ns) 9.700 ns fen24:u4\|tem2\[1\] 4 REG LC1_E35 6 " "Info: 4: + IC(2.300 ns) + CELL(0.000 ns) = 9.700 ns; Loc. = LC1_E35; Fanout = 6; REG Node = 'fen24:u4\|tem2\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.300 ns" { fen60:u3|carry fen24:u4|tem2[1] } "NODE_NAME" } } { "fen24.vhd" "" { Text "G:/clock/fen24.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 30.93 % ) " "Info: Total cell delay = 3.000 ns ( 30.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.700 ns ( 69.07 % ) " "Info: Total interconnect delay = 6.700 ns ( 69.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.700 ns" { clkin fen60:u2|carry fen60:u3|carry fen24:u4|tem2[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.700 ns" { clkin clkin~out fen60:u2|carry fen60:u3|carry fen24:u4|tem2[1] } { 0.000ns 0.000ns 0.400ns 4.000ns 2.300ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.700 ns" { clkin fen60:u2|carry fen60:u3|carry fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.700 ns" { clkin clkin~out fen60:u2|carry fen60:u3|carry fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.400ns 4.000ns 2.300ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.700 ns" { clkin fen60:u2|carry fen60:u3|carry fen24:u4|tem2[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.700 ns" { clkin clkin~out fen60:u2|carry fen60:u3|carry fen24:u4|tem2[1] } { 0.000ns 0.000ns 0.400ns 4.000ns 2.300ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "fen24.vhd" "" { Text "G:/clock/fen24.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.300 ns" { fen24:u4|tem2[1] fen24:u4|process0~60 fen24:u4|process0~57 fen24:u4|tem1~27 fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.300 ns" { fen24:u4|tem2[1] fen24:u4|process0~60 fen24:u4|process0~57 fen24:u4|tem1~27 fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.300ns 0.000ns 0.900ns 1.000ns } { 0.000ns 1.100ns 1.600ns 1.400ns 1.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.700 ns" { clkin fen60:u2|carry fen60:u3|carry fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.700 ns" { clkin clkin~out fen60:u2|carry fen60:u3|carry fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.400ns 4.000ns 2.300ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.700 ns" { clkin fen60:u2|carry fen60:u3|carry fen24:u4|tem2[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.700 ns" { clkin clkin~out fen60:u2|carry fen60:u3|carry fen24:u4|tem2[1] } { 0.000ns 0.000ns 0.400ns 4.000ns 2.300ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clkin seg5\[3\] fen24:u4\|lpm_counter:tem1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 21.200 ns register " "Info: tco from clock \"clkin\" to destination pin \"seg5\[3\]\" through register \"fen24:u4\|lpm_counter:tem1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]\" is 21.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 9.700 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to source register is 9.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clkin 1 CLK PIN_126 9 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 9; CLK Node = 'clkin'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "clk.vhd" "" { Text "G:/clock/clk.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns fen60:u2\|carry 2 REG LC1_F34 9 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_F34; Fanout = 9; REG Node = 'fen60:u2\|carry'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { clkin fen60:u2|carry } "NODE_NAME" } } { "fen60.vhd" "" { Text "G:/clock/fen60.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(0.500 ns) 7.400 ns fen60:u3\|carry 3 REG LC2_E6 11 " "Info: 3: + IC(4.000 ns) + CELL(0.500 ns) = 7.400 ns; Loc. = LC2_E6; Fanout = 11; REG Node = 'fen60:u3\|carry'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.500 ns" { fen60:u2|carry fen60:u3|carry } "NODE_NAME" } } { "fen60.vhd" "" { Text "G:/clock/fen60.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(0.000 ns) 9.700 ns fen24:u4\|lpm_counter:tem1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 4 REG LC2_E36 4 " "Info: 4: + IC(2.300 ns) + CELL(0.000 ns) = 9.700 ns; Loc. = LC2_E36; Fanout = 4; REG Node = 'fen24:u4\|lpm_counter:tem1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.300 ns" { fen60:u3|carry fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 30.93 % ) " "Info: Total cell delay = 3.000 ns ( 30.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.700 ns ( 69.07 % ) " "Info: Total interconnect delay = 6.700 ns ( 69.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.700 ns" { clkin fen60:u2|carry fen60:u3|carry fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.700 ns" { clkin clkin~out fen60:u2|carry fen60:u3|carry fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 0.400ns 4.000ns 2.300ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.000 ns + Longest register pin " "Info: + Longest register to pin delay is 11.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fen24:u4\|lpm_counter:tem1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 1 REG LC2_E36 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_E36; Fanout = 4; REG Node = 'fen24:u4\|lpm_counter:tem1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 1.700 ns seg5\[3\]~2 2 COMB LC4_E36 1 " "Info: 2: + IC(0.300 ns) + CELL(1.400 ns) = 1.700 ns; Loc. = LC4_E36; Fanout = 1; COMB Node = 'seg5\[3\]~2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.700 ns" { fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] seg5[3]~2 } "NODE_NAME" } } { "clk.vhd" "" { Text "G:/clock/clk.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(6.300 ns) 11.000 ns seg5\[3\] 3 PIN PIN_80 0 " "Info: 3: + IC(3.000 ns) + CELL(6.300 ns) = 11.000 ns; Loc. = PIN_80; Fanout = 0; PIN Node = 'seg5\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.300 ns" { seg5[3]~2 seg5[3] } "NODE_NAME" } } { "clk.vhd" "" { Text "G:/clock/clk.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.700 ns ( 70.00 % ) " "Info: Total cell delay = 7.700 ns ( 70.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 30.00 % ) " "Info: Total interconnect delay = 3.300 ns ( 30.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.000 ns" { fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] seg5[3]~2 seg5[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.000 ns" { fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] seg5[3]~2 seg5[3] } { 0.000ns 0.300ns 3.000ns } { 0.000ns 1.400ns 6.300ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.700 ns" { clkin fen60:u2|carry fen60:u3|carry fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.700 ns" { clkin clkin~out fen60:u2|carry fen60:u3|carry fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 0.400ns 4.000ns 2.300ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.000 ns" { fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] seg5[3]~2 seg5[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.000 ns" { fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] seg5[3]~2 seg5[3] } { 0.000ns 0.300ns 3.000ns } { 0.000ns 1.400ns 6.300ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 16 16:38:36 2009 " "Info: Processing ended: Thu Apr 16 16:38:36 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}