clk.fnsim.qmsg

一个时钟计数器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 16 16:40:14 2009 " "Info: Processing started: Thu Apr 16 16:40:14 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clk -c clk --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clk -c clk --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fen24.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fen24.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fen24-behave " "Info: Found design unit 1: fen24-behave" {  } { { "fen24.vhd" "" { Text "G:/clock/fen24.vhd" 24 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fen24 " "Info: Found entity 1: fen24" {  } { { "fen24.vhd" "" { Text "G:/clock/fen24.vhd" 17 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fen60.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fen60.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fen60-behave " "Info: Found design unit 1: fen60-behave" {  } { { "fen60.vhd" "" { Text "G:/clock/fen60.vhd" 26 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fen60 " "Info: Found entity 1: fen60" {  } { { "fen60.vhd" "" { Text "G:/clock/fen60.vhd" 17 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "second.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file second.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 second-behave " "Info: Found design unit 1: second-behave" {  } { { "second.vhd" "" { Text "G:/clock/second.vhd" 22 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 second " "Info: Found entity 1: second" {  } { { "second.vhd" "" { Text "G:/clock/second.vhd" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clk.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clk-one " "Info: Found design unit 1: clk-one" {  } { { "clk.vhd" "" { Text "G:/clock/clk.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clk " "Info: Found entity 1: clk" {  } { { "clk.vhd" "" { Text "G:/clock/clk.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clk " "Info: Elaborating entity \"clk\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fen60 fen60:u2 " "Info: Elaborating entity \"fen60\" for hierarchy \"fen60:u2\"" {  } { { "clk.vhd" "u2" { Text "G:/clock/clk.vhd" 36 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "tem1 fen60.vhd(46) " "Warning (10492): VHDL Process Statement warning at fen60.vhd(46): signal \"tem1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fen60.vhd" "" { Text "G:/clock/fen60.vhd" 46 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "tem2 fen60.vhd(47) " "Warning (10492): VHDL Process Statement warning at fen60.vhd(47): signal \"tem2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fen60.vhd" "" { Text "G:/clock/fen60.vhd" 47 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fen24 fen24:u4 " "Info: Elaborating entity \"fen24\" for hierarchy \"fen24:u4\"" {  } { { "clk.vhd" "u4" { Text "G:/clock/clk.vhd" 38 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "tem1 fen24.vhd(47) " "Warning (10492): VHDL Process Statement warning at fen24.vhd(47): signal \"tem1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fen24.vhd" "" { Text "G:/clock/fen24.vhd" 47 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "tem2 fen24.vhd(48) " "Warning (10492): VHDL Process Statement warning at fen24.vhd(48): signal \"tem2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fen24.vhd" "" { Text "G:/clock/fen24.vhd" 48 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "fen24:u4\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"fen24:u4\|lpm_add_sub:Add0\"" {  } { { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}