📄 clk.map.rpt
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; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+----------------+
; Resource ; Usage ;
+-----------------------------------+----------------+
; Total logic elements ; 40 ;
; Total combinational functions ; 37 ;
; -- Total 4-input functions ; 12 ;
; -- Total 3-input functions ; 11 ;
; -- Total 2-input functions ; 5 ;
; -- Total 1-input functions ; 9 ;
; -- Total 0-input functions ; 0 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 26 ;
; Total logic cells in carry chains ; 4 ;
; I/O pins ; 25 ;
; Maximum fan-out node ; fen60:u2|carry ;
; Maximum fan-out ; 9 ;
; Total fan-out ; 170 ;
; Average fan-out ; 2.62 ;
+-----------------------------------+----------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------------+
; |clk ; 40 (0) ; 26 ; 0 ; 25 ; 14 (0) ; 3 (0) ; 23 (0) ; 4 (0) ; 0 (0) ; |clk ;
; |fen24:u4| ; 14 (10) ; 8 ; 0 ; 0 ; 6 (6) ; 1 (1) ; 7 (3) ; 4 (0) ; 0 (0) ; |clk|fen24:u4 ;
; |lpm_counter:tem1_rtl_0| ; 4 (0) ; 4 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; 0 (0) ; |clk|fen24:u4|lpm_counter:tem1_rtl_0 ;
; |alt_counter_f10ke:wysi_counter| ; 4 (4) ; 4 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; 0 (0) ; |clk|fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter ;
; |fen60:u2| ; 13 (13) ; 9 ; 0 ; 0 ; 4 (4) ; 1 (1) ; 8 (8) ; 0 (0) ; 0 (0) ; |clk|fen60:u2 ;
; |fen60:u3| ; 13 (13) ; 9 ; 0 ; 0 ; 4 (4) ; 1 (1) ; 8 (8) ; 0 (0) ; 0 (0) ; |clk|fen60:u3 ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 26 ;
; Number of registers using Synchronous Clear ; 4 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 13 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: fen24:u4|lpm_counter:tem1_rtl_0 ;
+------------------------+-------------------+-------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------------+-------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 4 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+-------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Thu Apr 16 16:38:18 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clk -c clk
Info: Found 2 design units, including 1 entities, in source file fen24.vhd
Info: Found design unit 1: fen24-behave
Info: Found entity 1: fen24
Info: Found 2 design units, including 1 entities, in source file fen60.vhd
Info: Found design unit 1: fen60-behave
Info: Found entity 1: fen60
Info: Found 2 design units, including 1 entities, in source file second.vhd
Info: Found design unit 1: second-behave
Info: Found entity 1: second
Info: Found 2 design units, including 1 entities, in source file clk.vhd
Info: Found design unit 1: clk-one
Info: Found entity 1: clk
Info: Elaborating entity "clk" for the top level hierarchy
Info: Elaborating entity "fen60" for hierarchy "fen60:u2"
Warning (10492): VHDL Process Statement warning at fen60.vhd(46): signal "tem1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at fen60.vhd(47): signal "tem2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "fen24" for hierarchy "fen24:u4"
Warning (10492): VHDL Process Statement warning at fen24.vhd(47): signal "tem1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at fen24.vhd(48): signal "tem2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Inferred 1 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "fen24:u4|tem1[0]~12"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "fen24:u4|lpm_counter:tem1_rtl_0"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf
Info: Found entity 1: alt_counter_f10ke
Info: Elaborated megafunction instantiation "fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "fen24:u4|lpm_counter:tem1_rtl_0"
Info: Instantiated megafunction "fen24:u4|lpm_counter:tem1_rtl_0" with the following parameter:
Info: Parameter "LPM_WIDTH" = "4"
Info: Parameter "LPM_DIRECTION" = "UP"
Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Implemented 65 device resources after synthesis - the final resource count might be different
Info: Implemented 1 input pins
Info: Implemented 24 output pins
Info: Implemented 40 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
Info: Processing ended: Thu Apr 16 16:38:21 2009
Info: Elapsed time: 00:00:04
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