clk.map.summary

来自「一个时钟计数器」· SUMMARY 代码 · 共 10 行

Analysis & Synthesis Status : Successful - Thu Apr 16 16:38:21 2009
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : clk
Top-level Entity Name : clk
Family : ACEX1K
Total logic elements : 40
Total pins : 25
Total memory bits : 0
Total PLLs : 0