clk.tan.rpt

一个时钟计数器

; N/A   ; None         ; 18.700 ns  ; fen24:u4|tem2[3]                                                    ; seg6[3] ; clkin      ;
; N/A   ; None         ; 18.700 ns  ; fen24:u4|tem2[2]                                                    ; seg6[2] ; clkin      ;
; N/A   ; None         ; 14.400 ns  ; fen60:u3|tem2[3]                                                    ; seg4[3] ; clkin      ;
; N/A   ; None         ; 14.400 ns  ; fen60:u3|tem2[2]                                                    ; seg4[2] ; clkin      ;
; N/A   ; None         ; 14.400 ns  ; fen60:u3|tem2[1]                                                    ; seg4[1] ; clkin      ;
; N/A   ; None         ; 14.400 ns  ; fen60:u3|tem2[0]                                                    ; seg4[0] ; clkin      ;
; N/A   ; None         ; 14.400 ns  ; fen60:u3|tem1[3]                                                    ; seg3[3] ; clkin      ;
; N/A   ; None         ; 14.400 ns  ; fen60:u3|tem1[2]                                                    ; seg3[2] ; clkin      ;
; N/A   ; None         ; 14.400 ns  ; fen60:u3|tem1[1]                                                    ; seg3[1] ; clkin      ;
; N/A   ; None         ; 14.400 ns  ; fen60:u3|tem1[0]                                                    ; seg3[0] ; clkin      ;
; N/A   ; None         ; 10.400 ns  ; fen60:u2|tem1[3]                                                    ; seg1[3] ; clkin      ;
; N/A   ; None         ; 10.400 ns  ; fen60:u2|tem1[2]                                                    ; seg1[2] ; clkin      ;
; N/A   ; None         ; 10.400 ns  ; fen60:u2|tem1[1]                                                    ; seg1[1] ; clkin      ;
; N/A   ; None         ; 10.400 ns  ; fen60:u2|tem1[0]                                                    ; seg1[0] ; clkin      ;
; N/A   ; None         ; 9.900 ns   ; fen60:u2|tem2[3]                                                    ; seg2[3] ; clkin      ;
; N/A   ; None         ; 9.900 ns   ; fen60:u2|tem2[2]                                                    ; seg2[2] ; clkin      ;
; N/A   ; None         ; 9.900 ns   ; fen60:u2|tem2[1]                                                    ; seg2[1] ; clkin      ;
; N/A   ; None         ; 9.900 ns   ; fen60:u2|tem2[0]                                                    ; seg2[0] ; clkin      ;
+-------+--------------+------------+---------------------------------------------------------------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Apr 16 16:38:35 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clk -c clk
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clkin" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "fen60:u3|carry" as buffer
    Info: Detected ripple clock "fen60:u2|carry" as buffer
Info: Clock "clkin" has Internal fmax of 119.05 MHz between source register "fen24:u4|tem2[1]" and destination register "fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[0]" (period= 8.4 ns)
    Info: + Longest register to register delay is 7.300 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E35; Fanout = 6; REG Node = 'fen24:u4|tem2[1]'
        Info: 2: + IC(0.300 ns) + CELL(1.100 ns) = 1.400 ns; Loc. = LC6_E35; Fanout = 1; COMB Node = 'fen24:u4|process0~60'
        Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 3.000 ns; Loc. = LC7_E35; Fanout = 2; COMB Node = 'fen24:u4|process0~57'
        Info: 4: + IC(0.900 ns) + CELL(1.400 ns) = 5.300 ns; Loc. = LC3_E36; Fanout = 7; COMB Node = 'fen24:u4|tem1~27'
        Info: 5: + IC(1.000 ns) + CELL(1.000 ns) = 7.300 ns; Loc. = LC7_E34; Fanout = 6; REG Node = 'fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: Total cell delay = 5.100 ns ( 69.86 % )
        Info: Total interconnect delay = 2.200 ns ( 30.14 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clkin" to destination register is 9.700 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 9; CLK Node = 'clkin'
            Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_F34; Fanout = 9; REG Node = 'fen60:u2|carry'
            Info: 3: + IC(4.000 ns) + CELL(0.500 ns) = 7.400 ns; Loc. = LC2_E6; Fanout = 11; REG Node = 'fen60:u3|carry'
            Info: 4: + IC(2.300 ns) + CELL(0.000 ns) = 9.700 ns; Loc. = LC7_E34; Fanout = 6; REG Node = 'fen24:u4|lpm_counter:tem1_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
            Info: Total cell delay = 3.000 ns ( 30.93 % )
            Info: Total interconnect delay = 6.700 ns ( 69.07 % )
        Info: - Longest clock path from clock "clkin" to source register is 9.700 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 9; CLK Node = 'clkin'
            Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_F34; Fanout = 9; REG Node = 'fen60:u2|carry'
            Info: 3: + IC(4.000 ns) + CELL(0.500 ns) = 7.400 ns; Loc. = LC2_E6; Fanout = 11; REG Node = 'fen60:u3|carry'
            Info: 4: + IC(2.300 ns) + CELL(0.000 ns) = 9.700 ns; Loc. = LC1_E35; Fanout = 6; REG Node = 'fen24:u4|tem2[1]'
            Info: Total cell delay = 3.000 ns ( 30.93 % )
            Info: Total interconnect delay = 6.700 ns ( 69.07 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Micro setup delay of destination is 0.600 ns
Info: tco from