qwe.map.qmsg

3-8译码器和8-3BCD七段显示译码器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 22 21:51:09 2009 " "Info: Processing started: Wed Apr 22 21:51:09 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off qwe -c qwe " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off qwe -c qwe" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "E:/83/qwe.vhd " "Warning: Can't analyze file -- file E:/83/qwe.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file 1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 coder8_3-edc " "Info: Found design unit 1: coder8_3-edc" {  } { { "1.vhd" "" { Text "E:/83/1.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 coder8_3 " "Info: Found entity 1: coder8_3" {  } { { "1.vhd" "" { Text "E:/83/1.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "qwe.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file qwe.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 qwe " "Info: Found entity 1: qwe" {  } { { "qwe.bdf" "" { Schematic "E:/83/qwe.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "qwe " "Info: Elaborating entity \"qwe\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "coder8_3 coder8_3:inst " "Info: Elaborating entity \"coder8_3\" for hierarchy \"coder8_3:inst\"" {  } { { "qwe.bdf" "inst" { Schematic "E:/83/qwe.bdf" { { 64 336 456 160 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "18 " "Info: Implemented 18 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "7 " "Info: Implemented 7 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "7 " "Info: Implemented 7 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 22 21:51:14 2009 " "Info: Processing ended: Wed Apr 22 21:51:14 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}