📄 qwe.tan.rpt
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Timing Analyzer report for qwe
Wed Apr 22 21:52:32 2009
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 11.325 ns ; A[2] ; Y[0] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C20F484C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 11.325 ns ; A[2] ; Y[0] ;
; N/A ; None ; 11.280 ns ; A[2] ; Y[1] ;
; N/A ; None ; 11.267 ns ; A[2] ; Y[4] ;
; N/A ; None ; 11.200 ns ; A[2] ; Y[3] ;
; N/A ; None ; 11.190 ns ; A[2] ; Y[2] ;
; N/A ; None ; 11.118 ns ; A[0] ; Y[1] ;
; N/A ; None ; 11.116 ns ; A[0] ; Y[0] ;
; N/A ; None ; 11.096 ns ; A[0] ; Y[4] ;
; N/A ; None ; 11.031 ns ; A[1] ; Y[0] ;
; N/A ; None ; 11.022 ns ; A[1] ; Y[1] ;
; N/A ; None ; 10.996 ns ; A[1] ; Y[4] ;
; N/A ; None ; 10.995 ns ; A[0] ; Y[3] ;
; N/A ; None ; 10.984 ns ; A[0] ; Y[2] ;
; N/A ; None ; 10.910 ns ; A[1] ; Y[3] ;
; N/A ; None ; 10.905 ns ; A[2] ; Y[6] ;
; N/A ; None ; 10.888 ns ; A[2] ; Y[5] ;
; N/A ; None ; 10.887 ns ; A[1] ; Y[2] ;
; N/A ; None ; 10.708 ns ; A[0] ; Y[6] ;
; N/A ; None ; 10.684 ns ; A[0] ; Y[5] ;
; N/A ; None ; 10.594 ns ; A[1] ; Y[5] ;
; N/A ; None ; 10.579 ns ; A[1] ; Y[6] ;
; N/A ; None ; 10.543 ns ; A[3] ; Y[0] ;
; N/A ; None ; 10.542 ns ; A[3] ; Y[1] ;
; N/A ; None ; 10.520 ns ; A[3] ; Y[4] ;
; N/A ; None ; 10.423 ns ; A[3] ; Y[3] ;
; N/A ; None ; 10.408 ns ; A[3] ; Y[2] ;
; N/A ; None ; 10.132 ns ; A[3] ; Y[6] ;
; N/A ; None ; 10.110 ns ; A[3] ; Y[5] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Wed Apr 22 21:52:31 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off qwe -c qwe --timing_analysis_only
Info: Longest tpd from source pin "A[2]" to destination pin "Y[0]" is 11.325 ns
Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_T1; Fanout = 7; PIN Node = 'A[2]'
Info: 2: + IC(5.670 ns) + CELL(0.623 ns) = 7.228 ns; Loc. = LCCOMB_X1_Y9_N26; Fanout = 1; COMB Node = 'coder8_3:inst|Mux6~3'
Info: 3: + IC(1.051 ns) + CELL(3.046 ns) = 11.325 ns; Loc. = PIN_R2; Fanout = 0; PIN Node = 'Y[0]'
Info: Total cell delay = 4.604 ns ( 40.65 % )
Info: Total interconnect delay = 6.721 ns ( 59.35 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Wed Apr 22 21:52:32 2009
Info: Elapsed time: 00:00:02
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