rt28xx.h

ralink最新rt3070 usb wifi 无线网卡驱动程序

		UINT32       Bss0Key1CipherAlg:3;
		UINT32       :1;
		UINT32       Bss0Key2CipherAlg:3;
		UINT32       :1;
		UINT32       Bss0Key3CipherAlg:3;
		UINT32       :1;
		UINT32       Bss1Key0CipherAlg:3;
		UINT32       :1;
		UINT32       Bss1Key1CipherAlg:3;
		UINT32       :1;
		UINT32       Bss1Key2CipherAlg:3;
		UINT32       :1;
		UINT32       Bss1Key3CipherAlg:3;
		UINT32       :1;
	}	field;
	UINT32			word;
}	SHAREDKEY_MODE_STRUC, *PSHAREDKEY_MODE_STRUC;
#endif
// 64-entry for pairwise key table
typedef struct _HW_WCID_ENTRY {  // 8-byte per entry
    UCHAR   Address[6];
    UCHAR   Rsv[2];
} HW_WCID_ENTRY, PHW_WCID_ENTRY;



//
// Other on-chip shared memory space, base = 0x2000
//

// CIS space - base address = 0x2000
#define HW_CIS_BASE             0x2000

// Carrier-sense CTS frame base address. It's where mac stores carrier-sense frame for carrier-sense function.
#define HW_CS_CTS_BASE			0x7700
// DFS CTS frame base address. It's where mac stores CTS frame for DFS.
#define HW_DFS_CTS_BASE			0x7780
#define HW_CTS_FRAME_SIZE		0x80

// 2004-11-08 john - since NULL frame won't be that long (256 byte). We steal 16 tail bytes
// to save debugging settings
#define HW_DEBUG_SETTING_BASE   0x77f0  // 0x77f0~0x77ff total 16 bytes
#define HW_DEBUG_SETTING_BASE2   0x7770  // 0x77f0~0x77ff total 16 bytes

// In order to support maximum 8 MBSS and its maximum length is 512 for each beacon
// Three section discontinue memory segments will be used.
// 1. The original region for BCN 0~3
// 2. Extract memory from FCE table for BCN 4~5
// 3. Extract memory from Pair-wise key table for BCN 6~7
//	  It occupied those memory of wcid 238~253 for BCN 6 
//						      and wcid 222~237 for BCN 7  	
#define HW_BEACON_MAX_SIZE      0x1000 /* unit: byte */
#define HW_BEACON_BASE0         0x7800
#define HW_BEACON_BASE1         0x7A00
#define HW_BEACON_BASE2         0x7C00
#define HW_BEACON_BASE3         0x7E00
#define HW_BEACON_BASE4         0x7200
#define HW_BEACON_BASE5         0x7400
#define HW_BEACON_BASE6         0x5DC0
#define HW_BEACON_BASE7         0x5BC0

#define HW_BEACON_MAX_COUNT     8 
#define HW_BEACON_OFFSET		0x0200 
#define HW_BEACON_CONTENT_LEN	(HW_BEACON_OFFSET - TXWI_SIZE)

// HOST-MCU shared memory - base address = 0x2100
#define HOST_CMD_CSR		0x404
#define H2M_MAILBOX_CSR         0x7010
#define H2M_MAILBOX_CID         0x7014
#define H2M_MAILBOX_STATUS      0x701c
#define H2M_INT_SRC             0x7024
#define H2M_BBP_AGENT           0x7028
#define M2H_CMD_DONE_CSR        0x000c
#define MCU_TXOP_ARRAY_BASE     0x000c   // TODO: to be provided by Albert
#define MCU_TXOP_ENTRY_SIZE     32       // TODO: to be provided by Albert
#define MAX_NUM_OF_TXOP_ENTRY   16       // TODO: must be same with 8051 firmware
#define MCU_MBOX_VERSION        0x01     // TODO: to be confirmed by Albert
#define MCU_MBOX_VERSION_OFFSET 5        // TODO: to be provided by Albert

//
// Host DMA registers - base address 0x200 .  TX0-3=EDCAQid0-3, TX4=HCCA, TX5=MGMT,
//
//
//  DMA RING DESCRIPTOR
//
#define E2PROM_CSR          0x0004
#define IO_CNTL_CSR         0x77d0

#ifdef RT2870
// 8051 firmware image for usb - use last-half base address = 0x3000
#define FIRMWARE_IMAGE_BASE     0x3000
#define MAX_FIRMWARE_IMAGE_SIZE 0x1000    // 4kbyte
#endif // RT2870 //

// TODO: ????? old RT2560 registers. to keep them or remove them?
//#define MCAST0                  0x0178  // multicast filter register 0
//#define MCAST1                  0x017c  // multicast filter register 1


// ================================================================
// Tx /	Rx / Mgmt ring descriptor definition
// ================================================================

// the following PID values are used to mark outgoing frame type in TXD->PID so that
// proper TX statistics can be collected based on these categories
// b3-2 of PID field -
#define PID_MGMT			0x05
#define PID_BEACON			0x0c
#define PID_DATA_NORMALUCAST	 	0x02
#define PID_DATA_AMPDU	 	0x04
#define PID_DATA_NO_ACK    	0x08
#define PID_DATA_NOT_NORM_ACK	 	0x03
// value domain of pTxD->HostQId (4-bit: 0~15)
#define QID_AC_BK               1   // meet ACI definition in 802.11e
#define QID_AC_BE               0   // meet ACI definition in 802.11e
#define QID_AC_VI               2
#define QID_AC_VO               3
#define QID_HCCA                4
#define NUM_OF_TX_RING          5
#define QID_MGMT                13
#define QID_RX                  14
#define QID_OTHER               15


// ------------------------------------------------------
// BBP & RF	definition
// ------------------------------------------------------
#define	BUSY		                1
#define	IDLE		                0

#define	RF_R00					    0
#define	RF_R01					    1
#define	RF_R02					    2
#define	RF_R03					    3
#define	RF_R04					    4
#define	RF_R05					    5
#define	RF_R06					    6
#define	RF_R07					    7
#define	RF_R08					    8
#define	RF_R09					    9
#define	RF_R10					    10
#define	RF_R11					    11
#define	RF_R12					    12
#define	RF_R13					    13
#define	RF_R14					    14
#define	RF_R15					    15
#define	RF_R16					    16
#define	RF_R17					    17
#define	RF_R18					    18
#define	RF_R19					    19
#define	RF_R20					    20
#define	RF_R21					    21
#define	RF_R22					    22
#define	RF_R23					    23
#define	RF_R24					    24
#define	RF_R25					    25
#define	RF_R26					    26
#define	RF_R27					    27
#define	RF_R28					    28
#define	RF_R29					    29
#define	RF_R30					    30
#define	RF_R31					    31

#define	BBP_R0					    0  // version
#define	BBP_R1				        1  // TSSI
#define	BBP_R2          			2  // TX configure
#define BBP_R3                      3
#define BBP_R4                      4
#define BBP_R5                      5
#define BBP_R6                      6
#define	BBP_R14			            14 // RX configure
#define BBP_R16                     16
#define BBP_R17                     17 // RX sensibility
#define BBP_R18                     18
#define BBP_R21                     21
#define BBP_R22                     22
#define BBP_R24                     24
#define BBP_R25                     25
#define BBP_R31                     31
#define BBP_R49                     49 //TSSI
#define BBP_R50                     50
#define BBP_R51                     51
#define BBP_R52                     52
#define BBP_R55                     55
#define BBP_R62                     62 // Rx SQ0 Threshold HIGH
#define BBP_R63                     63
#define BBP_R64                     64
#define BBP_R65                     65
#define BBP_R66                     66
#define BBP_R67                     67
#define BBP_R68                     68
#define BBP_R69                     69
#define BBP_R70                     70 // Rx AGC SQ CCK Xcorr threshold
#define BBP_R73                     73
#define BBP_R75						75
#define BBP_R77                     77
#define BBP_R79                     79
#define BBP_R80                     80
#define BBP_R81                     81
#define BBP_R82                     82
#define BBP_R83                     83
#define BBP_R84                     84
#define BBP_R86						86
#define BBP_R91						91
#define BBP_R92						92
#define BBP_R94                     94 // Tx Gain Control
#define BBP_R103                    103
#define BBP_R105                    105
#define BBP_R113                    113
#define BBP_R114                    114
#define BBP_R115                    115
#define BBP_R116                    116
#define BBP_R117                    117
#define BBP_R118                    118
#define BBP_R119                    119
#define BBP_R120                    120
#define BBP_R121                    121
#define BBP_R122                    122
#define BBP_R123                    123
#ifdef RT30xx
#define BBP_R138                    138 // add by johnli, RF power sequence setup, ADC dynamic on/off control
#endif // RT30xx //


#define BBPR94_DEFAULT              0x06 // Add 1 value will gain 1db

//#define PHY_TR_SWITCH_TIME          5  // usec

//#define BBP_R17_LOW_SENSIBILITY     0x50
//#define BBP_R17_MID_SENSIBILITY     0x41
//#define BBP_R17_DYNAMIC_UP_BOUND    0x40
#define RSSI_FOR_VERY_LOW_SENSIBILITY -35
#define RSSI_FOR_LOW_SENSIBILITY      -58
#define RSSI_FOR_MID_LOW_SENSIBILITY  -80
#define RSSI_FOR_MID_SENSIBILITY      -90

//-------------------------------------------------------------------------
// EEPROM definition
//-------------------------------------------------------------------------
#define EEDO                        0x08
#define EEDI                        0x04
#define EECS                        0x02
#define EESK                        0x01
#define EERL                        0x80

#define EEPROM_WRITE_OPCODE         0x05
#define EEPROM_READ_OPCODE          0x06
#define EEPROM_EWDS_OPCODE          0x10
#define EEPROM_EWEN_OPCODE          0x13

#define	NUM_EEPROM_BBP_PARMS		19			// Include NIC Config 0, 1, CR, TX ALC step, BBPs
#define	NUM_EEPROM_TX_G_PARMS		7
#define	EEPROM_NIC1_OFFSET          0x34		// The address is from NIC config 0, not BBP register ID
#define	EEPROM_NIC2_OFFSET          0x36		// The address is from NIC config 0, not BBP register ID
#define	EEPROM_BBP_BASE_OFFSET		0xf0		// The address is from NIC config 0, not BBP register ID
#define	EEPROM_G_TX_PWR_OFFSET		0x52
#define	EEPROM_G_TX2_PWR_OFFSET		0x60
#define EEPROM_LED1_OFFSET			0x3c
#define EEPROM_LED2_OFFSET			0x3e
#define EEPROM_LED3_OFFSET			0x40
#define EEPROM_LNA_OFFSET			0x44
#define EEPROM_RSSI_BG_OFFSET		0x46
#define EEPROM_RSSI_A_OFFSET		0x4a
#define EEPROM_DEFINE_MAX_TXPWR		0x4e
#define EEPROM_TXPOWER_BYRATE_20MHZ_2_4G	0xde	// 20MHZ 2.4G tx power.
#define EEPROM_TXPOWER_BYRATE_40MHZ_2_4G	0xee	// 40MHZ 2.4G tx power.
#define EEPROM_TXPOWER_BYRATE_20MHZ_5G		0xfa	// 20MHZ 5G tx power.
#define EEPROM_TXPOWER_BYRATE_40MHZ_5G		0x10a	// 40MHZ 5G tx power.
#define EEPROM_A_TX_PWR_OFFSET      0x78
#define EEPROM_A_TX2_PWR_OFFSET      0xa6
//#define EEPROM_Japan_TX_PWR_OFFSET      0x90 // 802.11j
//#define EEPROM_Japan_TX2_PWR_OFFSET      0xbe
//#define EEPROM_TSSI_REF_OFFSET	0x54
//#define EEPROM_TSSI_DELTA_OFFSET	0x24
//#define EEPROM_CCK_TX_PWR_OFFSET  0x62
//#define EEPROM_CALIBRATE_OFFSET	0x7c
#define EEPROM_VERSION_OFFSET       0x02
#define	EEPROM_FREQ_OFFSET			0x3a
#define EEPROM_TXPOWER_BYRATE 	0xde	// 20MHZ power. 
#define EEPROM_TXPOWER_DELTA		0x50	// 20MHZ AND 40 MHZ use different power. This is delta in 40MHZ.
#define VALID_EEPROM_VERSION        1

// PairKeyMode definition
#define PKMODE_NONE                 0
#define PKMODE_WEP64                1
#define PKMODE_WEP128               2
#define PKMODE_TKIP                 3
#define PKMODE_AES                  4
#define PKMODE_CKIP64               5
#define PKMODE_CKIP128              6
#define PKMODE_TKIP_NO_MIC          7       // MIC appended by driver: not a valid value in hardware key table

// =================================================================================
// WCID  format
// =================================================================================
//7.1	WCID  ENTRY  format  : 8bytes
typedef	struct	_WCID_ENTRY_STRUC {
	UCHAR		RXBABitmap7;    // bit0 for TID8, bit7 for TID 15
	UCHAR		RXBABitmap0;    // bit0 for TID0, bit7 for TID 7
	UCHAR		MAC[6];	// 0 for shared key table.  1 for pairwise key table
}	WCID_ENTRY_STRUC, *PWCID_ENTRY_STRUC;

//8.1.1	SECURITY  KEY  format  : 8DW
// 32-byte per entry, total 16-entry for shared key table, 64-entry for pairwise key table
typedef struct _HW_KEY_ENTRY {          // 32-byte per entry
    UCHAR   Key[16];
    UCHAR   TxMic[8];
    UCHAR   RxMic[8];
} HW_KEY_ENTRY, *PHW_KEY_ENTRY; 

//8.1.2	IV/EIV  format  : 2DW

//8.1.3	RX attribute entry format  : 1DW
#ifdef RT_BIG_ENDIAN
typedef	struct	_MAC_ATTRIBUTE_STRUC {
	UINT32		rsv:22;
	UINT32		RXWIUDF:3;
	UINT32		BSSIDIdx:3; //multipleBSS index for the WCID
	UINT32		PairKeyMode:3;
	UINT32		KeyTab:1;	// 0 for shared key table.  1 for pairwise key table
}	MAC_ATTRIBUTE_STRUC, *PMAC_ATTRIBUTE_STRUC;
#else
typedef	struct	_MAC_ATTRIBUTE_STRUC {
	UINT32		KeyTab:1;	// 0 for shared key table.  1 for pairwise key table
	UINT32		PairKeyMode:3;
	UINT32		BSSIDIdx:3; //multipleBSS index for the WCID
	UINT32		RXWIUDF:3;
	UINT32		rsv:22;
}	MAC_ATTRIBUTE_STRUC, *PMAC_ATTRIBUTE_STRUC;
#endif


// =================================================================================
// TX / RX ring descriptor format
// =================================================================================

// the first 24-byte in TXD is called TXINFO and will be DMAed to MAC block through TXFIFO.
// MAC block use this TXINFO to control the transmission behavior of this frame.
#define FIFO_MGMT                 0
#define FIFO_HCCA                 1
#define FIFO_EDCA                 2

//
// TX descriptor format, Tx	ring, Mgmt Ring
//
#ifdef RT_BIG_ENDIAN
typedef	struct	PACKED _TXD_STRUC {
	// Word 0
	UINT32		SDPtr0;
	// Word 1
	UINT32		DMADONE:1;
	UINT32		LastSec0:1;
	UINT32		SDLen0:14;
	UINT32		Burst:1;
	UINT32		LastSec1:1;
	UINT32		SDLen1:14;
	// Word 2
	UINT32		SDPtr1;
	// Word 3
	UINT32		ICO:1;	
	UINT32		UCO:1;	
	UINT32		TCO:1;	
	UINT32		rsv:2;
	UINT32		QSEL:2;	// select on-chip FIFO ID for 2nd-stage output scheduler.0:MGMT, 1:HCCA 2:EDCA
	UINT32		WIV:1;	// Wireless Info Valid. 1 if Driver already fill WI,  o if DMA needs to copy WI to correctposition
	UINT32		rsv2:24;
}	TXD_STRUC, *PTXD_STRUC;
#else
typedef	struct	PACKED _TXD_STRUC {
	// Word	0
	UINT32		SDPtr0;
	// Word	1
	UINT32		SDLen1:14;
	UINT32		LastSec1:1;
	UINT32		Burst:1;
	UINT32		SDLen0:14;
	UINT32		LastSec0:1;
	UINT32		DMADONE:1;
	//Word2
	UINT32		SDPtr1;
	//Word3
	UINT32		rsv2:24;
	UINT32		WIV:1;	// Wireless Info Valid. 1 if Driver already fill WI,  o if DMA needs to copy WI to correctposition
	UINT32		QSEL:2;	// select on-chip FIFO ID for 2nd-stage output scheduler.0:MGMT, 1:HCCA 2:EDCA
	UINT32		rsv:2;
	UINT32		TCO:1;	//  
	UINT32		UCO:1;	//  
	UINT32		ICO:1;	//
}	TXD_STRUC, *PTXD_STRUC;
#endif


//
// TXD Wireless Information format for Tx ring and Mgmt Ring
//
//txop : for txop mode
// 0:txop for the MPDU frame will be handles by ASIC by register
// 1/2/3:the MPDU frame is send after PIFS/backoff/SIFS
#ifdef RT_BIG_ENDIAN
typedef	struct	PACKED _TXWI_STRUC {
	// Word 0
	UINT32		PHYMODE:2;
	UINT32		TxBF:1;	// 3*3
	UINT32		rsv2:1;
//	UINT32		rsv2:2;
	UINT32		Ifs:1;	// 
	UINT32		STBC:2;	//channel bandwidth 20MHz or 40 MHz
	UINT32		ShortGI:1;
	UINT32		BW:1;	//channel ban