📄 710defs.h
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******************************************************************************/
#define REG_GDMA_CTL0 (VPint(GDMA_BA+0x000)) /* Channel 0 Control Register */
#define REG_GDMA_SRCB0 (VPint(GDMA_BA+0x004)) /* Channel 0 Source Base Address Register */
#define REG_GDMA_DSTB0 (VPint(GDMA_BA+0x008)) /* Channel 0 Destination Base Address Register */
#define REG_GDMA_TCNT0 (VPint(GDMA_BA+0x00C)) /* Channel 0 Transfer Count Register */
#define REG_GDMA_CSRC0 (VPint(GDMA_BA+0x010)) /* Channel 0 Current Source Address Register */
#define REG_GDMA_CDST0 (VPint(GDMA_BA+0x014)) /* Channel 0 Current Destination Address Register */
#define REG_GDMA_CTCNT0 (VPint(GDMA_BA+0x018)) /* Channel 0 Current Transfer Count Register */
#define REG_GDMA_CTL1 (VPint(GDMA_BA+0x020)) /* Channel 1 Control Register */
#define REG_GDMA_SRCB1 (VPint(GDMA_BA+0x024)) /* Channel 1 Source Base Address Register */
#define REG_GDMA_DSTB1 (VPint(GDMA_BA+0x028)) /* Channel 1 Destination Base Address Register */
#define REG_GDMA_TCNT1 (VPint(GDMA_BA+0x02C)) /* Channel 1 Transfer Count Register */
#define REG_GDMA_CSRC1 (VPint(GDMA_BA+0x030)) /* Channel 1 Current Source Address Register */
#define REG_GDMA_CDST1 (VPint(GDMA_BA+0x034)) /* Channel 1 Current Destination Address Register */
#define REG_GDMA_CTCNT1 (VPint(GDMA_BA+0x038)) /* Channel 1 Current Transfer Count Register */
/******************************************************************************
*
* USB Host Controller Registers
*
******************************************************************************/
/* OpenHCI Registers */
#define REG_HcRevision (VPint(USBH_BA+0x000)) /* Host Controller Revision Register */
#define REG_HcControl (VPint(USBH_BA+0x004)) /* Host Controller Control Register */
#define REG_HcCommandStatus (VPint(USBH_BA+0x008)) /* Host Controller Command Status Register */
#define REG_HcInterruptStatus (VPint(USBH_BA+0x00C)) /* Host Controller Interrupt Status Register */
#define REG_HcInterruptEnable (VPint(USBH_BA+0x010)) /* Host Controller Interrupt Enable Register */
#define REG_HcInterruptDisable (VPint(USBH_BA+0x014)) /* Host Controller Interrupt Disable Register */
#define REG_HcHCCA (VPint(USBH_BA+0x018)) /* Host Controller Communication Area Register */
#define REG_HcPeriodCurrentED (VPint(USBH_BA+0x01C)) /* Host Controller Period Current ED Register */
#define REG_HcControlHeadED (VPint(USBH_BA+0x020)) /* Host Controller Control Head ED Register */
#define REG_HcControlCurrentED (VPint(USBH_BA+0x024)) /* Host Controller Control Current ED Register */
#define REG_HcBulkHeadED (VPint(USBH_BA+0x028)) /* Host Controller Bulk Head ED Register */
#define REG_HcBulkCurrentED (VPint(USBH_BA+0x02C)) /* Host Controller Bulk Current ED Register */
#define REG_HcDoneHead (VPint(USBH_BA+0x030)) /* Host Controller Done Head Register */
#define REG_HcFmInterval (VPint(USBH_BA+0x034)) /* Host Controller Frame Interval Register */
#define REG_HcFrameRemaining (VPint(USBH_BA+0x038)) /* Host Controller Frame Remaining Register */
#define REG_HcFmNumber (VPint(USBH_BA+0x03C)) /* Host Controller Frame Number Register */
#define REG_HcPeriodicStart (VPint(USBH_BA+0x040)) /* Host Controller Periodic Start Register */
#define REG_HcLSThreshold (VPint(USBH_BA+0x044)) /* Host Controller Low Speed Threshold Register */
#define REG_HcRhDescriptorA (VPint(USBH_BA+0x048)) /* Host Controller Root Hub Descriptor A Register */
#define REG_HcRhDescriptorB (VPint(USBH_BA+0x04C)) /* Host Controller Root Hub Descriptor B Register */
#define REG_HcRhStatus (VPint(USBH_BA+0x050)) /* Host Controller Root Hub Status Register */
#define REG_HcRhPortStatus1 (VPint(USBH_BA+0x054)) /* Host Controller Root Hub Port Status [1] */
#define REG_HcRhPortStatus2 (VPint(USBH_BA+0x058)) /* Host Controller Root Hub Port Status [2] */
/* USB Configuration Registers */
#define TestModeEnable (VPint(USBH_BA+0x200)) /* USB Test Mode Enable Register */
#define OperationalModeEnable (VPint(USBH_BA+0x204)) /* USB Operational Mode Enable Register */
/******************************************************************************
*
* USB Device Control Registers
*
******************************************************************************/
#define REG_USB_CTL (VPint(USBD_BA+0x000)) /* USB control register */
#define REG_USB_CVCMD (VPint(USBD_BA+0x004)) /* USB class or vendor command register */
#define REG_USB_IE (VPint(USBD_BA+0x008)) /* USB interrupt enable register */
#define REG_USB_IS (VPint(USBD_BA+0x00c)) /* USB interrupt status register */
#define REG_USB_IC (VPint(USBD_BA+0x010)) /* USB interrupt status clear register */
#define REG_USB_IFSTR (VPint(USBD_BA+0x014)) /* USB interface and string register */
#define REG_USB_ODATA0 (VPint(USBD_BA+0x018)) /* USB control transfer-out port 0 register */
#define REG_USB_ODATA1 (VPint(USBD_BA+0x01C)) /* USB control transfer-out port 1 register */
#define REG_USB_ODATA2 (VPint(USBD_BA+0x020)) /* USB control transfer-out port 2 register */
#define REG_USB_ODATA3 (VPint(USBD_BA+0x024)) /* USB control transfer-out port 3 register */
#define REG_USB_IDATA0 (VPint(USBD_BA+0x028)) /* USB control transfer-in data port 0 register */
#define REG_USB_IDATA1 (VPint(USBD_BA+0x02C)) /* USB control transfer-in data port 1 register */
#define REG_USB_IDATA2 (VPint(USBD_BA+0x030)) /* USB control transfer-in data port 2 register */
#define REG_USB_IDATA3 (VPint(USBD_BA+0x034)) /* USB control transfer-in data port 2 register */
#define REG_USB_SIE (VPint(USBD_BA+0x038)) /* USB SIE status Register */
#define REG_USB_ENG (VPint(USBD_BA+0x03c)) /* USB Engine Register */
#define REG_USB_CTLS (VPint(USBD_BA+0x040)) /* USB control transfer status register */
#define REG_USB_CONFD (VPint(USBD_BA+0x044)) /* USB Configured Value register */
#define REG_USB_EPA_INFO (VPint(USBD_BA+0x048)) /* USB endpoint A information register */
#define REG_USB_EPA_CTL (VPint(USBD_BA+0x04c)) /* USB endpoint A control register */
#define REG_USB_EPA_IE (VPint(USBD_BA+0x050)) /* USB endpoint A Interrupt Enable register */
#define REG_USB_EPA_IC (VPint(USBD_BA+0x054)) /* USB endpoint A interrupt clear register */
#define REG_USB_EPA_IS (VPint(USBD_BA+0x058)) /* USB endpoint A interrupt status register */
#define REG_USB_EPA_ADDR (VPint(USBD_BA+0x05c)) /* USB endpoint A address register */
#define REG_USB_EPA_LENTH (VPint(USBD_BA+0x060)) /* USB endpoint A transfer length register */
#define REG_USB_EPB_INFO (VPint(USBD_BA+0x064)) /* USB endpoint B information register */
#define REG_USB_EPB_CTL (VPint(USBD_BA+0x068)) /* USB endpoint B control register */
#define REG_USB_EPB_IE (VPint(USBD_BA+0x06c)) /* USB endpoint B Interrupt Enable register */
#define REG_USB_EPB_IC (VPint(USBD_BA+0x070)) /* USB endpoint B interrupt clear register */
#define REG_USB_EPB_IS (VPint(USBD_BA+0x074)) /* USB endpoint B interrupt status register */
#define REG_USB_EPB_ADDR (VPint(USBD_BA+0x078)) /* USB endpoint B address register */
#define REG_USB_EPB_LENTH (VPint(USBD_BA+0x07c)) /* USB endpoint B transfer length register */
#define REG_USB_EPC_INFO (VPint(USBD_BA+0x080)) /* USB endpoint C information register */
#define REG_USB_EPC_CTL (VPint(USBD_BA+0x084)) /* USB endpoint C control register */
#define REG_USB_EPC_IE (VPint(USBD_BA+0x088)) /* USB endpoint C Interrupt Enable register */
#define REG_USB_EPC_IC (VPint(USBD_BA+0x08c)) /* USB endpoint C interrupt clear register */
#define REG_USB_EPC_IS (VPint(USBD_BA+0x090)) /* USB endpoint C interrupt status register */
#define REG_USB_EPC_ADDR (VPint(USBD_BA+0x094)) /* USB endpoint C address register */
#define REG_USB_EPC_LENTH (VPint(USBD_BA+0x098)) /* USB endpoint C transfer length register */
#define REG_USB_EPA_XFER (VPint(USBD_BA+0x09c)) /* USB endpoint A remain transfer length register */
#define REG_USB_EPA_PKT (VPint(USBD_BA+0x0a0)) /* USB endpoint A remain packet length register */
#define REG_USB_EPB_XFER (VPint(USBD_BA+0x0a4)) /* USB endpoint B remain transfer length register */
#define REG_USB_EPB_PKT (VPint(USBD_BA+0x0a8)) /* USB endpoint B remain packet length register */
#define REG_USB_EPC_XFER (VPint(USBD_BA+0x0ac)) /* USB endpoint C remain transfer length register */
#define REG_USB_EPC_PKT (VPint(USBD_BA+0x0b0)) /* USB endpoint C remain packet length register */
/******************************************************************************
*
* Flash memory Card Control Registers
*
******************************************************************************/
/* Flash Memory Interface Registers definition */
#define REG_FMICR (VPint(FMI_BA+0x00)) /* FMI control register */
#define REG_FMIDSA (VPint(FMI_BA+0x04)) /* FMI DMA transfer starting address register */
#define REG_FMIBCR (VPint(FMI_BA+0x08)) /* FMI DMA byte count register */
#define REG_FMIIER (VPint(FMI_BA+0x0C)) /* FMI interrupt enable register */
#define REG_FMIISR (VPint(FMI_BA+0x10)) /* FMI interrupt status register */
#define REG_FMIBIST (VPint(FMI_BA+0x14)) /* FMI bist register */
#define REG_FB0_0 (VPint(FMI_BA+0x400)) /* Flash buffer 0 */
#define REG_FB1_0 (VPint(FMI_BA+0x800)) /* Flash buffer 1 */
/* Secure Digit Registers definition */
#define REG_SDCR (VPint(FMI_BA+0x300)) /* SD control register */
#define REG_SDHINI (VPint(FMI_BA+0x304)) /* SD host initial register */
#define REG_SDIER (VPint(FMI_BA+0x308)) /* SD interrupt enable register */
#define REG_SDISR (VPint(FMI_BA+0x30C)) /* SD interrupt status register */
#define REG_SDARG (VPint(FMI_BA+0x310)) /* SD command argument register */
#define REG_SDRSP0 (VPint(FMI_BA+0x314)) /* SD receive response token register 0 */
#define REG_SDRSP1 (VPint(FMI_BA+0x318)) /* SD receive response token register 1 */
#define REG_SDBLEN (VPint(FMI_BA+0x31C)) /* SD block length register */
/******************************************************************************
*
* Audio Interface Control Registers
*
******************************************************************************/
#define REG_ACTL_CON (VPint(ADO_BA + 0x00)) /* Audio controller control register */
#define REG_ACTL_RESET (VPint(ADO_BA + 0x04)) /* Sub block reset control register */
#define REG_ACTL_RDSTB (VPint(ADO_BA + 0x08)) /* DMA destination base address register for record */
#define REG_ACTL_RDST_LENGTH (VPint(ADO_BA + 0x0C)) /* DMA destination length register for record */
#define REG_ACTL_RDSTC (VPint(ADO_BA + 0x10)) /* DMA destination current address for record */
#define REG_ACTL_PDSTB (VPint(ADO_BA + 0x18)) /* DMA destination base address register for play */
#define REG_ACTL_PDST_LENGTH (VPint(ADO_BA + 0x1C)) /* DMA destination length register for play */
#define REG_ACTL_PDSTC (VPint(ADO_BA + 0x20)) /* DMA destination current address for play */
#define REG_ACTL_RSR (VPint(ADO_BA + 0x14)) /* Record status register */
#define REG_ACTL_PSR (VPint(ADO_BA + 0x24)) /* Play status register */
#define REG_ACTL_IISCON (VPint(ADO_BA + 0x28)) /* IIS control register */
#define REG_ACTL_ACCON (VPint(ADO_BA + 0x2C)) /* AC-link control register */
#define REG_ACTL_ACOS0 (VPint(ADO_BA + 0x30)) /* AC-link out slot 0 */
#define REG_ACTL_ACOS1 (VPint(ADO_BA + 0x34)) /* AC-link out slot 1 */
#define REG_ACTL_ACOS2 (VPint(ADO_BA + 0x38)) /* AC-link out slot 2 */
#define REG_ACTL_ACIS0 (VPint(ADO_BA + 0x3C)) /* AC-link in slot 0 */
#define REG_ACTL_ACIS1 (VPint(ADO_BA + 0x40)) /* AC-link in slot 1 */
#define REG_ACTL_ACIS2 (VPint(ADO_BA + 0x44)) /* AC-link in slot 2 */
#define REG_ACTL_ADCON (VPint(ADO_BA + 0x48)) /* ADC0 control register */
#define REG_ACTL_M80CON (VPint(ADO_BA + 0x4C)) /* M80 interface control register */
#define REG_ACTL_M80DATA0 (VPint(ADO_BA + 0x50)) /* M80 data0 register */
#define REG_ACTL_M80DATA1 (VPint(ADO_BA + 0x54)) /* M80 data1 register */
#define REG_ACTL_M80DATA2 (VPint(ADO_BA + 0x58)) /* M80 data2 register */
#define REG_ACTL_M80DATA3 (VPint(ADO_BA + 0x5C)) /* M80 data3 register */
#define REG_ACTL_M80ADDR (VPint(ADO_BA + 0x60)) /* M80 interface start address register */
#define REG_ACTL_M80SRADDR (VPint(ADO_BA + 0x64)) /* M80 interface start address register of right channel */
#define REG_ACTL_M80SIZE (VPint(ADO_BA + 0x70)) /* M80 interface data size register */
#define REG_ACTL_DACON (VPint(ADO_BA + 0x74)) /* DAC control register */
/******************************************************************************
*
* UART Control Registers
*
******************************************************************************/
/* UART 0 */
#define REG_UART_OFFSET 0x100
#define REG_UART0_TX (VPint(UART0_BA+0x0)) /* (VPint(W) TX buffer */
#define REG_UART0_RX (VPint(UART0_BA+0x0)) /* (R) RX buffer */
#define REG_UART0_LSB (VPint(UART0_BA+0x0)) /* Divisor latch LSB */
#define REG_UART0_MSB (VPint(UART0_BA+0x04)) /* Divisor latch MSB */
#define REG_UART0_IER (VPint(UART0_BA+0x04)) /* Interrupt enable register */
#define REG_UART0_IIR (VPint(UART0_BA+0x08)) /* (R) Interrupt ident. register */
#define REG_UART0_FCR (VPint(UART0_BA+0x08)) /* (W) FIFO control register */
#define REG_UART0_LCR (VPint(UART0_BA+0x0C)) /* Line control register */
#define REG_UART0_LSR (VPint(UART0_BA+0x14)) /* (R) Line status register */
#define REG_UART0_TOR (VPint(UART0_BA+0x1C)) /* (R) Time out register */
/* UART 1 */
#define REG_UART1_TX (VPint(UART1_BA+0x0)) /* (W) TX buffer */
#define REG_UART1_RX (VPint(UART1_BA+0x0)) /* (R) RX buffer */
#define REG_UART1_LSB (VPint(UART1_BA+0x0)) /* Divisor latch LSB */
#define REG_UART1_MSB (VPint(UART1_BA+0x04)) /* Divisor latch MSB */
#define REG_UART1_IER (VPint(UART1_BA+0x04)) /* Interrupt enable register */
#define REG_UART1_IIR (VPint(UART1_BA+0x08)) /* (R) Interrupt ident. register */
#define REG_UART1_FCR (VPint(UART1_BA+0x08)) /* (W) FIFO control register */
#define REG_UART1_LCR (VPint(UART1_BA+0x0C)) /* Line control register */
#define REG_UART1_MCR (VPint(UART1_BA+0x10)) /* Modem control register */
#define REG_UART1_LSR (VPint(UART1_BA+0x14)) /* (R) Line status register */
#define REG_UART1_MSR (VPint(UART1_BA+0x18)) /* (R) Modem status register */
#define REG_UART1_TOR (VPint(UART1_BA+0x1C)) /* (R) Time out register */
#define REG_UART1_UBCR (VPint(UART1_BA+0x20)) /* Bluetooth */
/* UART 2 */
#define REG_UART2_TX (VPint(UART2_BA+0x0) /* (W) TX buffer */
#define REG_UART2_RX (VPint(UART2_BA+0x0)) /* (R) RX buffer */
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