710defs.h

嵌入式编程

/******************************************************************************
* File Name			: 710defs.h
* Author			: 
* Date				:
* Version			: 
* Description		: This file contains the register map of W90P710 processor.
******************************************************************************/
#ifndef _W90P710_H
#define _W90P710_H

/******************************************************************************
*                                                               
* Data Types  
*
******************************************************************************/
#define CONST		const

#define FALSE		0
#define TRUE		1

#define S8			signed char
#define U8			unsigned char
#define S16			signed short
#define U16			unsigned short
#define S32			signed int
#define U32			unsigned int
#define BYTE		U8
#define HALF		U16
#define WORD		U32

typedef char              BOOL;
typedef char *            PBOOL;

typedef char              INT8;
typedef char *            PINT8;
typedef unsigned char     UINT8;
typedef unsigned char *   PUINT8;
typedef char *            PSTR;
typedef const char *      PCSTR;

typedef short             INT16;
typedef short *           PINT16;
typedef unsigned short    UINT16;
typedef unsigned short *  PUINT16;

typedef signed long       INT32;
typedef int *             PINT32;
typedef unsigned long     UINT32;
typedef unsigned int *    PUINT32;

typedef __int64           INT64;
typedef unsigned __int64  UINT64;

typedef float             FLOAT32;
typedef float *           PFLOAT32;

typedef double            DOUBLE64;
typedef double *          PDOUBLE32;


/* OSC freq. */
#define CrystalClk		15000000
#define PllClk			80000000				

/******************************************************************************
*                                                               
* I/O routines  
*
******************************************************************************/
#define VPint			*(unsigned int volatile *)
#define VPshort			*(unsigned short volatile *)
#define VPchar			*(unsigned char volatile *)


/******************************************************************************
*
* System Address Map - Defines the register base address of each Macro
*                         function.
******************************************************************************/
#define    GCR_BA    0xFFF00000 /* Global Control */
#define    EBI_BA    0xFFF01000 /* EBI Control */
#define    CACHE_BA  0xFFF02000 /* Cache Control */
#define    EMC_BA    0xFFF03000 /* Ethernet MAC */
#define    GDMA_BA   0xFFF04000 /* GDMA control */
#define    USBH_BA   0xFFF05000 /* USB Host Control */
#define    USBD_BA   0xFFF06000 /* USB Device Control */
#define    FMI_BA    0xFFF07000 /* Flash Memory Card Interface */
#define    LCD_BA    0xFFF08000 /* Display, LCM Interface & Bypass */
#define    ADO_BA    0xFFF09000 /* Audio Control */

#define    UART0_BA  0xFFF80000 /* UART0 Control (console) */
#define    UART1_BA  0xFFF80100 /* UART1 Control (Bluetooth) */
#define    UART2_BA  0xFFF80200 /* UART2 Control (IrDA) */
#define    UART3_BA  0xFFF80300 /* UART3 Control (micro-printer) */
#define    TMR_BA    0xFFF81000 /* Timer */
#define    AIC_BA    0xFFF82000 /* Interrupt Controller */
#define    GPIO_BA   0xFFF83000 /* GPIO Control */
#define    RTC_BA	 0xFFF84000 /* Real Time Clock Control */
#define    SCHI0_BA  0xFFF85000 /* Smart Card Host Interface 0 Control */
#define	   SCHI1_BA	 0xFFF85800 /* Smart Card Host Interface 1 Control */
#define    I2C0_BA   0xFFF86000 /* I2C 0 Control */
#define    I2C1_BA   0xFFF86100 /* I2C 1 Control */
#define    SSP_BA    0xFFF86200 /* Synchronous Serial Port */
#define    PWM_BA    0xFFF87000 /* Pulse Width Modulation Control */
#define    KPI_BA    0xFFF88000 /* Keypad Interface Control */
#define    PS2_BA    0xFFF89000 /* PS2 Interface Control */


/******************************************************************************
*
* System Manager Control Registers
*
******************************************************************************/
#define REG_PDID		(VPint(GCR_BA+0x0000))	/* Product Identifier Register  */
#define REG_ARBCON		(VPint(GCR_BA+0x0004))	/* Arbitration Control Register */
#define REG_PLLCON		(VPint(GCR_BA+0x0008))	/* PLL Control Register */
#define REG_CLKSEL		(VPint(GCR_BA+0x000C))	/* Clock Select Register */
#define REG_PLLCON2		(VPint(GCR_BA+0x0010))	/* PLL Control Register 2 */
#define REG_I2SCKCON	(VPint(GCR_BA+0x0014))	/* Audio IIS Clock Control Register */
#define REG_IRQWAKECON	(VPint(GCR_BA+0x0020))	/* IRQ Wakeup Control Register */
#define REG_IRQWAKEFLAG	(VPint(GCR_BA+0x0024))	/* IRQ Wakeup Flag Register */
#define REG_PMCON		(VPint(GCR_BA+0x0028))	/* Power Manager control Register */
#define REG_USBTXRCON	(VPint(GCR_BA+0x0030))	/* USB transceiver control Register */


/******************************************************************************
*
* Memory Control Registers
*
******************************************************************************/
#define REG_EBICON		(VPint(EBI_BA+0x000))	/* EBI control register */
#define REG_ROMCON		(VPint(EBI_BA+0x004))	/* ROM/FLASH control register */
#define REG_SDCONF0		(VPint(EBI_BA+0x008))	/* SDRAM bank 0 configuration register */
#define REG_SDCONF1		(VPint(EBI_BA+0x00C))	/* SDRAM bank 1 configuration register */
#define REG_SDTIME0		(VPint(EBI_BA+0x010))	/* SDRAM bank 0 timing control register */
#define REG_SDTIME1		(VPint(EBI_BA+0x014))	/* SDRAM bank 1 timing control register */
#define REG_EXT0CON		(VPint(EBI_BA+0x018))	/* External I/O 0 control register */
#define REG_EXT1CON		(VPint(EBI_BA+0x01C))	/* External I/O 1 control register */
#define REG_EXT2CON		(VPint(EBI_BA+0x020))	/* External I/O 2 control register */
#define REG_EXT3CON		(VPint(EBI_BA+0x024))	/* External I/O 3 control register */


/******************************************************************************
*
* Cache Control Registers
*
******************************************************************************/
#define REG_CAHCNF		(VPint(CACHE_BA+0x000))	/* Cache configuration register */
#define REG_CAHCON		(VPint(CACHE_BA+0x004))	/* Cache control register */
#define REG_CAHADR		(VPint(CACHE_BA+0x008))	/* Cache address register */


/******************************************************************************
*
* MAC Registers
*
******************************************************************************/
/* Control register */
#define REG_CAMCMR			(VPint(EMC_BA+0x000))	/* CAM Command Register */
#define REG_CAMEN			(VPint(EMC_BA+0x004))	/* CAM Enable Register */
#define REG_CAM0M_Base		(VPint(EMC_BA+0x008))
#define REG_CAM0L_Base		(VPint(EMC_BA+0x00c))
#define REG_CAMxM_Reg(x)	(VPint(REG_CAM0M_Base+x*0x8))
#define REG_CAMxL_Reg(x)	(VPint(REG_CAM0L_Base+x*0x8))

#define REG_TXDLSA			(VPint(EMC_BA+0x088))	/* Transmit Descriptor Link List Start Address Register */
#define REG_RXDLSA			(VPint(EMC_BA+0x08C))	/* Receive Descriptor Link List Start Address Register */
#define REG_MCMDR			(VPint(EMC_BA+0x090))	/* MAC Command Register */
#define REG_MIID			(VPint(EMC_BA+0x094))	/* MII Management Data Register */
#define REG_MIIDA			(VPint(EMC_BA+0x098))	/* MII Management Control and Address Register */
#define REG_FFTCR			(VPint(EMC_BA+0x09C))	/* FIFO Threshold Control Register */
#define REG_TSDR			(VPint(EMC_BA+0x0a0))	/* Transmit Start Demand Register */
#define REG_RSDR			(VPint(EMC_BA+0x0a4))	/* Receive Start Demand Register */
#define REG_DMARFC			(VPint(EMC_BA+0x0a8))	/* Maximum Receive Frame Control Register */
#define REG_MIEN			(VPint(EMC_BA+0x0ac))	/* MAC Interrupt Enable Register */
/* Status Registers */
#define REG_MISTA			(VPint(EMC_BA+0x0b0))	/* MAC Interrupt Status Register */
#define REG_MGSTA			(VPint(EMC_BA+0x0b4))	/* MAC General Status Register */
#define REG_MPCNT			(VPint(EMC_BA+0x0b8))	/* Missed Packet Count Register */
#define REG_MRPC			(VPint(EMC_BA+0x0bc))	/* MAC Receive Pause Count Register */
#define REG_MRPCC			(VPint(EMC_BA+0x0c0))	/* MAC Receive Pause Current Count Register */
#define REG_MREPC			(VPint(EMC_BA+0x0c4))	/* MAC Remote Pause Count Register */
#define REG_DMARFS			(VPint(EMC_BA+0x0c8))	/* DMA Receive Frame Status Register */
#define REG_CTXDSA			(VPint(EMC_BA+0x0cc))	/* Current Transmit Descriptor Start Address Register */
#define REG_CTXBSA			(VPint(EMC_BA+0x0d0))	/* Current Transmit Buffer Start Address Register */
#define REG_CRXDSA			(VPint(EMC_BA+0x0d4))	/* Current Receive Descriptor Start Address Register */
#define REG_CRXBSA			(VPint(EMC_BA+0x0d8))	/* Current Receive Buffer Start Address Register */
/* Diagnostic Registers */
#define REG_RXFSM			(VPint(EMC_BA+0x200))	/* Receive Finite State Machine Register */
#define REG_TXFSM			(VPint(EMC_BA+0x204))	/* Transmit Finite State Machine Register */
#define REG_FSM0			(VPint(EMC_BA+0x208))	/* Finite State Machine Register 0 */
#define REG_FSM1			(VPint(EMC_BA+0x20c))	/* Finite State Machine Register 1 */
#define REG_DCR				(VPint(EMC_BA+0x210))	/* Debug Configuration Register */
#define REG_DMMIR			(VPint(EMC_BA+0x214))	/* Debug Mode MAC Information Register */
#define REG_BISTR			(VPint(EMC_BA+0x300))	/* BIST Mode Register */


/******************************************************************************
*
* GDMA Registers
*