📄 710defs.h
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/* groups 6 */
#define REG_GPIO_CFG6 (VPint(GPIO_BA+0x0060)) /* GPIO port6 configuration Register */
#define REG_GPIO_DIR6 (VPint(GPIO_BA+0x0064)) /* GPIO port6 direction control Register */
#define REG_GPIO_DATAOUT6 (VPint(GPIO_BA+0x0068)) /* GPIO port6 data out Register */
#define REG_GPIO_DATAIN6 (VPint(GPIO_BA+0x006c)) /* GPIO port6 data input Register */
#define REG_GPIO_DBNCECON (VPint(GPIO_BA+0x0070)) /* GPIO input debounce control Register */
#define REG_GPIO_XICFG (VPint(GPIO_BA+0x0074)) /* Extend Interrupt Configure Register */
#define REG_GPIO_XISTATUS (VPint(GPIO_BA+0x0078)) /* Extend Interrupt Status Register */
/******************************************************************************
*
* PS2 Controller Registers
*
******************************************************************************/
#define REG_PS2CMD (VPint(PS2_BA+0x0000))
#define REG_PS2STS (VPint(PS2_BA+0x0004))
#define REG_PS2SCANCODE (VPint(PS2_BA+0x0008))
#define REG_PS2ASCII (VPint(PS2_BA+0x000c))
/******************************************************************************
*
* I2C Controller Registers
*
******************************************************************************/
#define REG_I2C_OFFSET 0x100
#define I2C_CSR (0x00)
#define I2C_DIVIDER (0x04)
#define I2C_CMDR (0x08)
#define I2C_SWR (0x0C)
#define I2C_RxR (0x10)
#define I2C_TxR (0x14)
#define REG_I2C_CSR0 (VPint(I2C0_BA+0x00))
#define REG_I2C_DIVIDER0 (VPint(I2C0_BA+0x04))
#define REG_I2C_CMDR0 (VPint(I2C0_BA+0x08))
#define REG_I2C_SWR0 (VPint(I2C0_BA+0x0C))
#define REG_I2C_RxR0 (VPint(I2C0_BA+0x10))
#define REG_I2C_TxR0 (VPint(I2C0_BA+0x14))
#define REG_I2C_CSR1 (VPint(I2C1_BA+0x00))
#define REG_I2C_DIVIDER1 (VPint(I2C1_BA+0x04))
#define REG_I2C_CMDR1 (VPint(I2C1_BA+0x08))
#define REG_I2C_SWR1 (VPint(I2C1_BA+0x0C))
#define REG_I2C_RxR1 (VPint(I2C1_BA+0x10))
#define REG_I2C_TxR1 (VPint(I2C1_BA+0x14))
/******************************************************************************
*
* Smart Card Host Interface Registers
*
******************************************************************************/
/* register offset from SCHI base address*/
/* BDLAB = 0 */
#define SC_RBR (0x00)
#define SC_TBR (0x00)
#define SC_IER (0x04)
#define SC_ISR (0x08)
#define SC_SCFR (0x08)
#define SC_SCCR (0x0c)
#define SC_CBR (0x10)
#define SC_SCSR (0x14)
#define SC_GTR (0x18)
#define SC_ECR (0x1c)
#define SC_TMR (0x20)
#define SC_TOC (0x28)
#define SC_TOIR0 (0x2c)
#define SC_TOIR1 (0x30)
#define SC_TOIR2 (0x34)
#define SC_TOD0 (0x38)
#define SC_TOD1 (0x3c)
#define SC_TOD2 (0x40)
#define SC_BTOR (0x44)
/* BDLAB = 1 */
#define SC_BLL (0x00)
#define SC_BLH (0x04)
#define SC_SCIDNR (0x08)
#define REG_SCHI_RBR0 (VPint(SCHI0_BA+SC_RBR))
#define REG_SCHI_TBR0 (VPint(SCHI0_BA+SC_TBR))
#define REG_SCHI_IER0 (VPint(SCHI0_BA+SC_IER))
#define REG_SCHI_ISR0 (VPint(SCHI0_BA+SC_ISR))
#define REG_SCHI_SCFR0 (VPint(SCHI0_BA+SC_SCFR))
#define REG_SCHI_SCCR0 (VPint(SCHI0_BA+SC_SCCR))
#define REG_SCHI_CBR0 (VPint(SCHI0_BA+SC_CBR))
#define REG_SCHI_SCSR0 (VPint(SCHI0_BA+SC_SCSR))
#define REG_SCHI_GTR0 (VPint(SCHI0_BA+SC_GTR))
#define REG_SCHI_ECR0 (VPint(SCHI0_BA+SC_ECR))
#define REG_SCHI_TMR0 (VPint(SCHI0_BA+SC_TMR))
#define REG_SCHI_TOC0 (VPint(SCHI0_BA+SC_TOC))
#define REG_SCHI_TOIR0_0 (VPint(SCHI0_BA+SC_TOIR0))
#define REG_SCHI_TOIR1_0 (VPint(SCHI0_BA+SC_TOIR1))
#define REG_SCHI_TOIR2_0 (VPint(SCHI0_BA+SC_TOIR2))
#define REG_SCHI_TOD0_0 (VPint(SCHI0_BA+SC_TOD0))
#define REG_SCHI_TOD1_0 (VPint(SCHI0_BA+SC_TOD1))
#define REG_SCHI_TOD2_0 (VPint(SCHI0_BA+SC_TOD2))
#define REG_SCHI_BTOR_0 (VPint(SCHI0_BA+SC_BTOR))
#define REG_SCHI_BLL_0 (VPint(SCHI0_BA+SC_BLL))
#define REG_SCHI_BLH_0 (VPint(SCHI0_BA+SC_BLH))
#define REG_SCHI_ID_0 (VPint(SCHI0_BA+SC_SCIDNR))
#define REG_SCHI_RBR1 (VPint(SCHI1_BA+SC_RBR))
#define REG_SCHI_TBR1 (VPint(SCHI1_BA+SC_TBR))
#define REG_SCHI_IER1 (VPint(SCHI1_BA+SC_IER))
#define REG_SCHI_ISR1 (VPint(SCHI1_BA+SC_ISR))
#define REG_SCHI_SCFR1 (VPint(SCHI1_BA+SC_SCFR))
#define REG_SCHI_SCCR1 (VPint(SCHI1_BA+SC_SCCR))
#define REG_SCHI_CBR1 (VPint(SCHI1_BA+SC_CBR))
#define REG_SCHI_SCSR1 (VPint(SCHI1_BA+SC_SCSR))
#define REG_SCHI_GTR1 (VPint(SCHI1_BA+SC_GTR))
#define REG_SCHI_ECR1 (VPint(SCHI1_BA+SC_ECR))
#define REG_SCHI_TMR1 (VPint(SCHI1_BA+SC_TMR))
#define REG_SCHI_TOC1 (VPint(SCHI1_BA+SC_TOC))
#define REG_SCHI_TOIR0_1 (VPint(SCHI1_BA+SC_TOIR0))
#define REG_SCHI_TOIR1_1 (VPint(SCHI1_BA+SC_TOIR1))
#define REG_SCHI_TOIR2_1 (VPint(SCHI1_BA+SC_TOIR2))
#define REG_SCHI_TOD0_1 (VPint(SCHI1_BA+SC_TOD0))
#define REG_SCHI_TOD1_1 (VPint(SCHI1_BA+SC_TOD1))
#define REG_SCHI_TOD2_1 (VPint(SCHI1_BA+SC_TOD2))
#define REG_SCHI_BTOR_1 (VPint(SCHI1_BA+SC_BTOR))
#define REG_SCHI_BLL_1 (VPint(SCHI1_BA+SC_BLL))
#define REG_SCHI_BLH_1 (VPint(SCHI1_BA+SC_BLH))
#define REG_SCHI_ID_1 (VPint(SCHI1_BA+SC_SCIDNR))
/******************************************************************************
*
* 710 LCD Controller Register Sets
*
******************************************************************************/
/* LCD Controller */
#define REG_LCD_LCDCON (VPint(LCD_BA+0x0000)) /* LCD Controller control register */
/* LCD Interrupt Control */
#define REG_LCD_LCDINTENB (VPint(LCD_BA+0x0004)) /* LCD interrupt enable register */
#define REG_LCD_LCDINTS (VPint(LCD_BA+0x0008)) /* LCD interrupt status register */
#define REG_LCD_LCDINTC (VPint(LCD_BA+0x000C)) /* LCD interrupt clear register */
/* LCD Pre-processing */
#define REG_LCD_OSDUPSCF (VPint(LCD_BA+0x0010)) /* OSD data Horizontal/Vertical up-scaling factor */
#define REG_LCD_VDUPSCF (VPint(LCD_BA+0x0014)) /* Video data Horizontal/Vertical up-scaling factor */
#define REG_LCD_OSDNSCF (VPint(LCD_BA+0x0018)) /* OSD data Horizontal/Vertical down-scaling factor */
#define REG_LCD_VDDNSCF (VPint(LCD_BA+0x001C)) /* Video data Horizontal/Vertical down-scaling factor */
/* LCD FIFO Control */
#define REG_LCD_FIFOCON (VPint(LCD_BA+0x0020)) /* LCD FIFOs controller register */
#define REG_LCD_FIFOSTATUS (VPint(LCD_BA+0x0024)) /* LCD FIFOs status register */
#define REG_LCD_FIFO1PRM (VPint(LCD_BA+0x0028)) /* LCD FIFO1 transfer parameters */
#define REG_LCD_FIFO2PRM (VPint(LCD_BA+0x002C)) /* LCD FIFO2 transfer parameters */
#define REG_LCD_F1SADDR (VPint(LCD_BA+0x0030)) /* FIFO1 transfer data source start address */
#define REG_LCD_F2SADDR (VPint(LCD_BA+0x0034)) /* FIFO2 transfer data source start address */
#define REG_LCD_F1DREQCNT (VPint(LCD_BA+0x0038)) /* FIFO1 transfer data count register */
#define REG_LCD_F2DREQCNT (VPint(LCD_BA+0x003C)) /* FIFO2 transfer data count register */
#define REG_LCD_F1CURADR (VPint(LCD_BA+0x0040)) /* FIFO1 current access data address register */
#define REG_LCD_F2CURADR (VPint(LCD_BA+0x0044)) /* FIFO2 current access data address register */
#define REG_LCD_FIFO1RELACOLCNT (VPint(LCD_BA+0x0048)) /* FIFO 1 real column count register */
#define REG_LCD_FIFO2RELACOLCNT (VPint(LCD_BA+0x004C)) /* FIFO 2 real column count register */
/* Color Generation */
#define REG_LCD_LUTENTY1 (VPint(LCD_BA+0x0050)) /* TFT: lookup table entry index register */
#define REG_LCD_LUTENTY2 (VPint(LCD_BA+0x0054)) /* TFT: lookup table entry index register */
#define REG_LCD_LUTENTY3 (VPint(LCD_BA+0x0058)) /* TFT: lookup table entry index register */
#define REG_LCD_LUTENTY4 (VPint(LCD_BA+0x005C)) /* TFT: lookup table entry index register */
#define REG_LCD_OSDLUTENTY1 (VPint(LCD_BA+0x0060)) /* TFT: lookup table entry index register */
#define REG_LCD_OSDLUTENTY2 (VPint(LCD_BA+0x0064)) /* TFT: lookup table entry index register */
#define REG_LCD_OSDLUTENTY3 (VPint(LCD_BA+0x0068)) /* TFT: lookup table entry index register */
#define REG_LCD_OSDLUTENTY4 (VPint(LCD_BA+0x006C)) /* TFT: lookup table entry index register */
#define REG_LCD_TMDDITHP1 (VPint(LCD_BA+0x0070)) /* Gray level dithered data duty pattern */
#define REG_LCD_TMDDITHP2 (VPint(LCD_BA+0x0074)) /* Gray level dithered data duty pattern */
#define REG_LCD_TMDDITHP3 (VPint(LCD_BA+0x0078)) /* Gray level dithered data duty pattern */
#define REG_LCD_TMDDITHP4 (VPint(LCD_BA+0x007C)) /* Gray level dithered data duty pattern */
#define REG_LCD_TMDDITHP5 (VPint(LCD_BA+0x0080)) /* Gray level dithered data duty pattern */
#define REG_LCD_TMDDITHP6 (VPint(LCD_BA+0x0084)) /* Gray level dithered data duty pattern */
#define REG_LCD_TMDDITHP7 (VPint(LCD_BA+0x0088)) /* Gray level dithered data duty pattern */
/* LCD Post-processing */
#define REG_LCD_DDISPCP (VPint(LCD_BA+0x0090)) /* Dummy Display Color Pattern Register */
#define REG_LCD_DISPWINS (VPint(LCD_BA+0x0094)) /* Valid Display Window Starting Coordinate */
#define REG_LCD_DISPWINE (VPint(LCD_BA+0x0098)) /* Valid Display Window Ending Coordinate */
#define REG_LCD_OSDWINS (VPint(LCD_BA+0x009C)) /* OSD Window Starting Coordinate */
#define REG_LCD_OSDWINE (VPint(LCD_BA+0x00A0)) /* OSD Window Ending Coordinate */
#define REG_LCD_OSDOVCN (VPint(LCD_BA+0x00A4)) /* OSD Overlay Control Register */
#define REG_LCD_OSDKYP (VPint(LCD_BA+0x00A8)) /* OSD Overlay Color-Key Pattern */
#define REG_LCD_OSDKYM (VPint(LCD_BA+0x00AC)) /* OSD Overlay Color-Key Mask */
/* LCD Timing Generation */
#define REG_LCD_LCDTCON1 (VPint(LCD_BA+0x00B0)) /* LCD Timing Control Register 1 */
#define REG_LCD_LCDTCON2 (VPint(LCD_BA+0x00B4)) /* LCD Timing Control Register 2 */
#define REG_LCD_LCDTCON3 (VPint(LCD_BA+0x00B8)) /* LCD Timing Control Register 3 */
#define REG_LCD_LCDTCON4 (VPint(LCD_BA+0x00BC)) /* LCD Timing Control Register 4 */
#define REG_LCD_LCDTCON5 (VPint(LCD_BA+0x00C0)) /* LCD Timing Control Register 5 */
#define REG_LCD_LCDTCON6 (VPint(LCD_BA+0x00C4)) /* LCD Timing Control Register 6 */
/* Look Up Table SRAM */
#define REG_LCD_LUTADDR (VPint(LCD_BA+0x0100)) /* The start address of Look-Up Table.
The memory range is 0x100 ~ 0x4FF. */
#endif /* _W90P710_H */
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