710defs.h

嵌入式编程

#define REG_UART2_LSB    (VPint(UART2_BA+0x0))    /* Divisor latch LSB */
#define REG_UART2_MSB    (VPint(UART2_BA+0x04))   /* Divisor latch MSB */
#define REG_UART2_IER    (VPint(UART2_BA+0x04))   /* Interrupt enable register */
#define REG_UART2_IIR    (VPint(UART2_BA+0x08))   /* (R) Interrupt ident. register */
#define REG_UART2_FCR    (VPint(UART2_BA+0x08))   /* (W) FIFO control register */
#define REG_UART2_LCR    (VPint(UART2_BA+0x0C))   /* Line control register */
#define	REG_UART2_LSR    (VPint(UART2_BA+0x14))   /* (R) Line status register */
#define	REG_UART2_TOR    (VPint(UART2_BA+0x1C))   /* (R) Time out register */
#define REG_UART2_IRCR   (VPint(UART2_BA+0x20))  /* (R/W) IrDA control register */

/* UART 3 */
#define REG_UART3_TX     (VPint(UART3_BA+0x0))    /* (W) TX buffer */
#define REG_UART3_RX     (VPint(UART3_BA+0x0))    /* (R) RX buffer */
#define REG_UART3_LSB    (VPint(UART3_BA+0x0))    /* Divisor latch LSB */
#define REG_UART3_MSB    (VPint(UART3_BA+0x04))   /* Divisor latch MSB */
#define REG_UART3_IER    (VPint(UART3_BA+0x04))   /* Interrupt enable register */
#define REG_UART3_IIR    (VPint(UART3_BA+0x08))   /* (R) Interrupt ident. register */
#define REG_UART3_FCR    (VPint(UART3_BA+0x08))   /* (W) FIFO control register */
#define REG_UART3_LCR    (VPint(UART3_BA+0x0C))   /* Line control register */
#define REG_UART3_MCR    (VPint(UART3_BA+0x10))   /* Modem control register */
#define	REG_UART3_LSR    (VPint(UART3_BA+0x14))   /* (R) Line status register */
#define REG_UART3_MSR    (VPint(UART3_BA+0x18))   /* (R) Modem status register */
#define	REG_UART3_TOR    (VPint(UART3_BA+0x1C))   /* (R) Time out register */


/******************************************************************************
*
* Timer Control Registers
*
******************************************************************************/
#define	REG_TCR0     (VPint(TMR_BA+0x0))    /* Control Register 0 */
#define	REG_TCR1     (VPint(TMR_BA+0x04))   /* Control Register 1 */
#define	REG_TICR0    (VPint(TMR_BA+0x08))   /* Initial Control Register 0 */
#define	REG_TICR1    (VPint(TMR_BA+0x0C))   /* Initial Control Register 1 */
#define	REG_TDR0     (VPint(TMR_BA+0x10))   /* Data Register 0 */
#define	REG_TDR1     (VPint(TMR_BA+0x14))   /* Data Register 1 */
#define	REG_TISR     (VPint(TMR_BA+0x18))   /* Interrupt Status Register */
#define REG_WTCR     (VPint(TMR_BA+0x1C))   /* Watchdog Timer Control Register */

/******************************************************************************
*
* Advanced Interrupt Controller Registers
*
******************************************************************************/
#define REG_AIC_SCR1    (VPint(AIC_BA+0x04))    /* Source control register 1 */
#define REG_AIC_SCR2    (VPint(AIC_BA+0x08))    /* Source control register 2 */
#define REG_AIC_SCR3    (VPint(AIC_BA+0x0C))    /* Source control register 3 */
#define REG_AIC_SCR4    (VPint(AIC_BA+0x10))    /* Source control register 4 */
#define REG_AIC_SCR5    (VPint(AIC_BA+0x14))    /* Source control register 5 */
#define REG_AIC_SCR6    (VPint(AIC_BA+0x18))    /* Source control register 6 */
#define REG_AIC_SCR7    (VPint(AIC_BA+0x1C))    /* Source control register 7 */
#define REG_AIC_SCR8    (VPint(AIC_BA+0x20))    /* Source control register 8 */
#define REG_AIC_SCR9    (VPint(AIC_BA+0x24))    /* Source control register 9 */
#define REG_AIC_SCR10   (VPint(AIC_BA+0x28))    /* Source control register 10 */
#define REG_AIC_SCR11   (VPint(AIC_BA+0x2C))    /* Source control register 11 */
#define REG_AIC_SCR12   (VPint(AIC_BA+0x30))    /* Source control register 12 */
#define REG_AIC_SCR13   (VPint(AIC_BA+0x34))    /* Source control register 13 */
#define REG_AIC_SCR14   (VPint(AIC_BA+0x38))    /* Source control register 14 */
#define REG_AIC_SCR15   (VPint(AIC_BA+0x3C))    /* Source control register 15 */
#define REG_AIC_SCR16   (VPint(AIC_BA+0x40))    /* Source control register 16 */
#define REG_AIC_SCR17   (VPint(AIC_BA+0x44))    /* Source control register 17 */
#define REG_AIC_SCR18   (VPint(AIC_BA+0x48))    /* Source control register 18 */
#define REG_AIC_SCR19   (VPint(AIC_BA+0x4C))    /* Source control register 19 */
#define REG_AIC_SCR20   (VPint(AIC_BA+0x50))    /* Source control register 20 */
#define REG_AIC_SCR21   (VPint(AIC_BA+0x54))    /* Source control register 21 */
#define REG_AIC_SCR22   (VPint(AIC_BA+0x58))    /* Source control register 22 */
#define REG_AIC_SCR23   (VPint(AIC_BA+0x5C))    /* Source control register 23 */
#define REG_AIC_SCR24   (VPint(AIC_BA+0x60))    /* Source control register 24 */
#define REG_AIC_SCR25   (VPint(AIC_BA+0x64))    /* Source control register 25 */
#define REG_AIC_SCR26   (VPint(AIC_BA+0x68))    /* Source control register 26 */
#define REG_AIC_SCR27   (VPint(AIC_BA+0x6c))    /* Source control register 27 */
#define REG_AIC_SCR28   (VPint(AIC_BA+0x70))    /* Source control register 28 */
#define REG_AIC_SCR29   (VPint(AIC_BA+0x74))    /* Source control register 29 */
#define REG_AIC_SCR30   (VPint(AIC_BA+0x78))    /* Source control register 30 */
#define REG_AIC_SCR31   (VPint(AIC_BA+0x7c))    /* Source control register 31 */

#define REG_AIC_IRSR    (VPint(AIC_BA+0x100))   /* Interrupt raw status register */
#define REG_AIC_IASR    (VPint(AIC_BA+0x104))   /* Interrupt active status register */
#define REG_AIC_ISR     (VPint(AIC_BA+0x108))   /* Interrupt status register */
#define REG_AIC_IPER    (VPint(AIC_BA+0x10C))   /* Interrupt priority encoding register */
#define REG_AIC_ISNR    (VPint(AIC_BA+0x110))   /* Interrupt source number register */
#define REG_AIC_IMR     (VPint(AIC_BA+0x114))   /* Interrupt mask register */
#define REG_AIC_OISR    (VPint(AIC_BA+0x118))   /* Output interrupt status register */
#define REG_AIC_MECR    (VPint(AIC_BA+0x120))   /* Mask enable command register */
#define REG_AIC_MDCR    (VPint(AIC_BA+0x124))   /* Mask disable command register */
#define REG_AIC_SSCR    (VPint(AIC_BA+0x128))   /* Source set command register */
#define REG_AIC_SCCR    (VPint(AIC_BA+0x12C))   /* Source clear command register */
#define REG_AIC_EOSCR   (VPint(AIC_BA+0x130))   /* End of service command register */
#define REG_AIC_TEST    (VPint(AIC_BA+0x200))   /* ICE/Debug mode register */


/******************************************************************************
*
* Universal Serial Interface Control Registers
*
******************************************************************************/
#define	REG_USI_CNTRL		(VPint(SSP_BA+0x0))     /* Control and Status Register */
#define	REG_USI_DIVIDER		(VPint(SSP_BA+0x04))    /* Clock Divider Register */
#define	REG_USI_SSR			(VPint(SSP_BA+0x08))    /* Slave Select Register */
#define	REG_USI_Rx0			(VPint(SSP_BA+0x10))    /* Data Receive Register 0 */
#define	REG_USI_Rx1			(VPint(SSP_BA+0x14))    /* Data Receive Register 1 */
#define	REG_USI_Rx2			(VPint(SSP_BA+0x18))    /* Data Receive Register 2 */
#define	REG_USI_Rx3			(VPint(SSP_BA+0x1C))    /* Data Receive Register 3 */
#define	REG_USI_Tx0			(VPint(SSP_BA+0x10))    /* Data Transmit Register 0 */
#define	REG_USI_Tx1			(VPint(SSP_BA+0x14))    /* Data Transmit Register 1 */
#define	REG_USI_Tx2			(VPint(SSP_BA+0x18))    /* Data Transmit Register 2 */
#define	REG_USI_Tx3			(VPint(SSP_BA+0x1C))    /* Data Transmit Register 3 */


/******************************************************************************
*
* RTC Control Registers
*
******************************************************************************/
#define REG_RTC_INIR		(VPint(RTC_BA+0x0000))	/* Product RTC RTC INITIALION Register  */
#define REG_RTC_AER			(VPint(RTC_BA+0x0004))	/* Product RTC RTC ACCESS ENABLE Register  */
#define REG_RTC_FCR			(VPint(RTC_BA+0x0008))	/* Product RTC RTC FREQUENCY COMPENSATION Register  */
#define REG_RTC_TLR			(VPint(RTC_BA+0x000C))	/* Product RTC TIME LOADING Register  */
#define REG_RTC_CLR			(VPint(RTC_BA+0x0010))	/* Product RTC CALENDAR LOADING Register  */
#define REG_RTC_TSSR		(VPint(RTC_BA+0x0014))	/* Product RTC TIME SCAL SELECTION Register  */
#define REG_RTC_DWR			(VPint(RTC_BA+0x0018))	/* Product RTC DAY OF THE WEEK Register  */
#define REG_RTC_TAR			(VPint(RTC_BA+0x001C))	/* Product RTC TIME ALARM Register  */
#define REG_RTC_CAR			(VPint(RTC_BA+0x0020))	/* Product RTC CALENDAR ALARM Register  */
#define REG_RTC_LIR			(VPint(RTC_BA+0x0024))	/* Product RTC LEAP YEAR INDICATOR Register  */
#define REG_RTC_RIER		(VPint(RTC_BA+0x0028))	/* Product RTC RTC INTERRUPT ENABLE Register  */
#define REG_RTC_RIIR		(VPint(RTC_BA+0x002C))	/* Product RTC RTC INTERRUPT INDICATOR Register  */
#define REG_RTC_TTR			(VPint(RTC_BA+0x0030))	/* Product RTC RTC TIME TICK Register  */


/******************************************************************************
*
* PWM Control Registers
*
******************************************************************************/
#define REG_PWM_OFFSET	    0xC
#define REG_PWM_PPR			(VPint(PWM_BA+0x0000))
#define REG_PWM_CSR			(VPint(PWM_BA+0x0004))
#define REG_PWM_PCR			(VPint(PWM_BA+0x0008))
#define REG_PWM_CNR0		(VPint(PWM_BA+0x000C))
#define REG_PWM_CMR0		(VPint(PWM_BA+0x0010))
#define REG_PWM_PDR0		(VPint(PWM_BA+0x0014))
#define REG_PWM_CNR1		(VPint(PWM_BA+0x0018))
#define REG_PWM_CMR1		(VPint(PWM_BA+0x001C))
#define REG_PWM_PDR1		(VPint(PWM_BA+0x0020))
#define REG_PWM_CNR2		(VPint(PWM_BA+0x0024))
#define REG_PWM_CMR2		(VPint(PWM_BA+0x0028))
#define REG_PWM_PDR2		(VPint(PWM_BA+0x002C))
#define REG_PWM_CNR3		(VPint(PWM_BA+0x0030))
#define REG_PWM_CMR3		(VPint(PWM_BA+0x0034))
#define REG_PWM_PDR3		(VPint(PWM_BA+0x0038))
#define REG_PWM_PIER		(VPint(PWM_BA+0x003C))
#define REG_PWM_PIIR		(VPint(PWM_BA+0x0040))


/******************************************************************************
*
* Keypad Interface Registers
*
******************************************************************************/
#define REG_KPICONF			(VPint(KPI_BA+0x0000))	/* Product  KPI controller configuration Register  */
#define REG_KPI3KCONF		(VPint(KPI_BA+0x0004))	/* Product  KPI controller 3-keys configuration Register  */
#define REG_KPILPCONF		(VPint(KPI_BA+0x0008))	/* Product  KPI controller low power configuration Register  */
#define REG_KPISTATUS		(VPint(KPI_BA+0x000C))	/* Product  KPI controller status Register  */


/******************************************************************************
*
* General-Purpose Input/Output Controller Registers
*
******************************************************************************/
#define REG_GPIO_OFFSET			0x10
/* groups 0 */
#define REG_GPIO_CFG0			(VPint(GPIO_BA+0x0000))	/* GPIO port0 configuration Register  */
#define REG_GPIO_DIR0			(VPint(GPIO_BA+0x0004))	/* GPIO port0 direction control Register  */
#define REG_GPIO_DATAOUT0		(VPint(GPIO_BA+0x0008))	/* GPIO port0 data out Register  */
#define REG_GPIO_DATAIN0        (VPint(GPIO_BA+0x000c))	/* GPIO port0 data input Register */
/* groups 1 */
#define REG_GPIO_CFG1			(VPint(GPIO_BA+0x0010))	/* GPIO port1 configuration Register  */
#define REG_GPIO_DIR1			(VPint(GPIO_BA+0x0014))	/* GPIO port1 direction control Register  */
#define REG_GPIO_DATAOUT1		(VPint(GPIO_BA+0x0018))	/* GPIO port1 data out Register  */
#define REG_GPIO_DATAIN1        (VPint(GPIO_BA+0x001c))	/* GPIO port1 data input Register */
/* groups 2 */
#define REG_GPIO_CFG2			(VPint(GPIO_BA+0x0020))	/* GPIO port2 configuration Register  */
#define REG_GPIO_DIR2			(VPint(GPIO_BA+0x0024))	/* GPIO port2 direction control Register  */
#define REG_GPIO_DATAOUT2		(VPint(GPIO_BA+0x0028))	/* GPIO port2 data out Register  */
#define REG_GPIO_DATAIN2        (VPint(GPIO_BA+0x002c))	/* GPIO port2 data input Register */
/* groups 3 */
#define REG_GPIO_CFG3			(VPint(GPIO_BA+0x0030))	/* GPIO port3 configuration Register  */
#define REG_GPIO_DIR3			(VPint(GPIO_BA+0x0034))	/* GPIO port3 direction control Register  */
#define REG_GPIO_DATAOUT3		(VPint(GPIO_BA+0x0038))	/* GPIO port3 data out Register  */
#define REG_GPIO_DATAIN3        (VPint(GPIO_BA+0x003c))	/* GPIO port3 data input Register */
/* groups 4 */
#define REG_GPIO_CFG4			(VPint(GPIO_BA+0x0040))	/* GPIO port4 configuration Register  */
#define REG_GPIO_DIR4			(VPint(GPIO_BA+0x0044))	/* GPIO port4 direction control Register  */
#define REG_GPIO_DATAOUT4		(VPint(GPIO_BA+0x0048))	/* GPIO port4 data out Register  */
#define REG_GPIO_DATAIN4        (VPint(GPIO_BA+0x004c))	/* GPIO port4 data input Register */
/* groups 5 */
#define REG_GPIO_CFG5			(VPint(GPIO_BA+0x0050))	/* GPIO port5 configuration Register  */
#define REG_GPIO_DIR5			(VPint(GPIO_BA+0x0054))	/* GPIO port5 direction control Register  */
#define REG_GPIO_DATAOUT5		(VPint(GPIO_BA+0x0058))	/* GPIO port5 data out Register  */
#define REG_GPIO_DATAIN5        (VPint(GPIO_BA+0x005c))	/* GPIO port5 data input Register */