system_10inch.h

TFT LCD驱动芯片T100A+AU7" Source code

//---------------------------------------------------------------------------
// Terawins Inc. Company Confidential Strictly Private
//
// $Archive: System.h $
// $Revision: 1.0 $
// $Author: JoannW $
// $Date: 2002/06/18 $
//
// --------------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------------
// Copyright 2002(c) Terawins Inc.
// This is an unpublished work.
// --------------------------------------------------------------------------

#if !defined(__SYSTEM_H__)
#define __SYSTEM_H__
//***************************************************************
//Test
//***************************************************************
#define DISPLAY_FUNC

#define WVGA
//#define WXGA

#define TV
//	#define PAL
	#define NTSC
#define PAL_I  0x0e
#define PAL_DK 0x0f
//***************************************************************
//Test
//***************************************************************
#define DELAY_LINES  4
//***************************************************************
//Source
//***************************************************************
typedef enum{
	isrcTV    =0x01,
	isrcCVIDEO2,
	isrcCVIDEO3,
	isrcCVIDEO4,
	isrcSVIDEO,

    isrc_T515_CVIDEO1,
    isrc_T515_CVIDEO2,
    isrc_T515_SVIDEO,
	isrc_end,
	isrcCOMPONENT

}VIDEOINPUT;
//***************************************************************
//define Port
//***************************************************************
sbit 	BKLIGHT_EN		= P0^7;

sbit	AUDIO_MUTE		= P1^3;
sbit	CHIP_RESET      = P1^4;
sbit 	VIDEO_RESET		= P1^5;//P0^2; //P1^3;

sbit 	LED_GREEN		= P2^6;
sbit 	LED_RED		    = P2^7;
/************************************
         System
************************************/
#define TIMER0
#define INTERRUPT1
#define TIMER1

#define XCLK			27000000 

#ifdef KVGA
#define DFDIV_40		47	 	//40MHz

#define DIDIV			2    	//0xC9
#define DODIV			2    	//0xCA
#endif

#ifdef WVGA
#define DFDIV_40		47	 	//40MHz

#define DIDIV			2    	//0xC9
#define DODIV			2    	//0xCA
#endif
#ifdef WXGA
#define DFDIV_40		46	 	//40MHz

#define DIDIV			2    	//0xC9
#define DODIV			1    	//0xCA
#endif

#define DRDIV			(1<<(DODIV+1))
#define DNDIV_40		((float)(DFDIV_40+2)/(DIDIV+2)/DRDIV)


#define BACKLIGHT
#define POWER_ON_SEQUENCE

#define NVRAM

/************************************
         Display
************************************/
#define TCON
//#define RSDS
//#define AUDIO_AVAILABLE
//#define INTERLACED
//#define TMDS

#ifdef AUDIO_AVAILABLE
	#define VPWME	0x10
	#define PVOL_BGHS_SEL	0x04
#else
	#define VPWME	0x00
	#define PVOL_BGHS_SEL 	0x00
#endif

#ifdef TMDS
	#define TMDS_LOW		39000000
	#define TMDS_HIGH       80000000
#endif

//#define	TCONPOWER			1 //this if for chip bug May.08
#ifdef TCON
  	#define	TCONPOWER		1
	#define TCON_GO_SYNC 	1
#else
  	#define	TCONPOWER		0
	#define TCON_GO_SYNC 	0
#endif


#define DIGITAL_BRIGHT
#define DIGITAL_CONTRAST

#define GAMMA_EN
#ifdef GAMMA_EN
	#define GAMMAR_ONLY
	#define GAMMAG_ONLY
	#define GAMMAB_ONLY
	#define GAMMARGB_TOGETHER
#endif

#define FAILSAFE_EN
#ifdef FAILSAFE_EN
	#define VSYNC_MAX		85
#endif

//#define INTERLACED
/************************************
         Input Source
************************************/
#define VIDEO_AVAILABLE				1
#define TV_AVAILABLE				1
/************************************
         Software Config
************************************/
#define FAILSAFE_ADJ_EN
	#define FAILSAFE_ADJ_POS 		0x01
	#define FAILSAFE_ADJ_FREQ		0x02
	#define FAILSAFE_ADJ_PHASE		0x04
#define SUBSAMPLE_ADJ_EN
	#define SUBSAMPLE_ADJ_POS		0x01
	#define SUBSAMPLE_ADJ_FREQ		0x02
	#define SUBSAMPLE_ADJ_PHASE		0x04
#define DUBLESAMPLE_ADJ_EN
	#define DUBLESAMPLE_ADJ_POS		0x01
	#define DUBLESAMPLE_ADJ_FREQ	0x02
	#define DUBLESAMPLE_ADJ_PHASE	0x04
//#define DOSMODE_ADJ_EN
	#define DOSMODE_ADJ_POS			0x01
	#define DOSMODE_ADJ_FREQ      	0x02
	#define DOSMODE_ADJ_PHASE      	0x04

#define	GM_RGB_ALL_SAME
#define ADJ_DIGITAL				1
#define ADJ_ADC					0


#endif // __SYSTEM_H__