📄 e-try.sim.rpt
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; |E-TRY|div:inst6|fre_N[4] ; |E-TRY|div:inst6|fre_N[4]~141COUT1_151 ; cout1 ;
; |E-TRY|div:inst1|fre_N[5] ; |E-TRY|div:inst1|fre_N[5]~140 ; cout0 ;
; |E-TRY|div:inst1|fre_N[6] ; |E-TRY|div:inst1|fre_N[6]~144 ; cout0 ;
; |E-TRY|div:inst7|fre_N[23] ; |E-TRY|div:inst7|fre_N[23]~380 ; cout0 ;
; |E-TRY|div:inst7|fre_N[23] ; |E-TRY|div:inst7|fre_N[23]~380COUT1_498 ; cout1 ;
; |E-TRY|div:inst7|fre_N[17] ; |E-TRY|div:inst7|fre_N[17]~384 ; cout0 ;
; |E-TRY|div:inst7|fre_N[18] ; |E-TRY|div:inst7|fre_N[18]~392 ; cout0 ;
; |E-TRY|div:inst7|fre_N[19] ; |E-TRY|div:inst7|fre_N[19]~396 ; cout0 ;
; |E-TRY|div:inst7|fre_N[15] ; |E-TRY|div:inst7|fre_N[15]~404COUT1_492 ; cout1 ;
; |E-TRY|div:inst7|fre_N[20] ; |E-TRY|div:inst7|fre_N[20]~408 ; cout0 ;
; |E-TRY|div:inst7|fre_N[20] ; |E-TRY|div:inst7|fre_N[20]~408COUT1_496 ; cout1 ;
; |E-TRY|div:inst7|fre_N[21] ; |E-TRY|div:inst7|fre_N[21]~412 ; cout ;
; |E-TRY|div:inst7|fre_N[22] ; |E-TRY|div:inst7|fre_N[22]~416 ; cout0 ;
; |E-TRY|div:inst7|fre_N[22] ; |E-TRY|div:inst7|fre_N[22]~416COUT1_497 ; cout1 ;
; |E-TRY|div:inst7|LessThan~591 ; |E-TRY|div:inst7|LessThan~591 ; combout ;
; |E-TRY|div:inst7|fre_N[2] ; |E-TRY|div:inst7|fre_N[2]~428COUT1_481 ; cout1 ;
; |E-TRY|div:inst7|fre_N[3] ; |E-TRY|div:inst7|fre_N[3]~432COUT1_482 ; cout1 ;
; |E-TRY|div:inst7|fre_N[4] ; |E-TRY|div:inst7|fre_N[4]~436COUT1_483 ; cout1 ;
; |E-TRY|div:inst7|fre_N[5] ; |E-TRY|div:inst7|fre_N[5]~440COUT1_484 ; cout1 ;
; |E-TRY|div:inst7|fre_N[7] ; |E-TRY|div:inst7|fre_N[7]~444 ; cout0 ;
; |E-TRY|div:inst7|fre_N[8] ; |E-TRY|div:inst7|fre_N[8]~448 ; cout0 ;
; |E-TRY|div:inst7|fre_N[9] ; |E-TRY|div:inst7|fre_N[9]~452 ; cout0 ;
; |E-TRY|div:inst7|fre_N[10] ; |E-TRY|div:inst7|fre_N[10]~456 ; cout0 ;
; |E-TRY|div:inst7|fre_N[12] ; |E-TRY|div:inst7|fre_N[12]~468COUT1_489 ; cout1 ;
; |E-TRY|div:inst7|fre_N[13] ; |E-TRY|div:inst7|fre_N[13]~472COUT1_490 ; cout1 ;
; |E-TRY|div:inst7|fre_N[14] ; |E-TRY|div:inst7|fre_N[14]~476COUT1_491 ; cout1 ;
; |E-TRY|div:inst7|LessThan~597 ; |E-TRY|div:inst7|LessThan~597 ; combout ;
; |E-TRY|div:inst7|LessThan~598 ; |E-TRY|div:inst7|LessThan~598 ; combout ;
; |E-TRY|FPGA_7279:inst|key_7279_tmp[7] ; |E-TRY|FPGA_7279:inst|key_7279_tmp[7] ; regout ;
; |E-TRY|FPGA_7279:inst|sdata_cnt[0] ; |E-TRY|FPGA_7279:inst|sdata_cnt[0] ; regout ;
; |E-TRY|FPGA_7279:inst|LessThan~111 ; |E-TRY|FPGA_7279:inst|LessThan~111 ; combout ;
; |E-TRY|FPGA_7279:inst|key_7279[7]~54 ; |E-TRY|FPGA_7279:inst|key_7279[7]~54 ; combout ;
; |E-TRY|FPGA_7279:inst|key_7279_tmp[6] ; |E-TRY|FPGA_7279:inst|key_7279_tmp[6] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279_tmp[5] ; |E-TRY|FPGA_7279:inst|key_7279_tmp[5] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279_tmp[4] ; |E-TRY|FPGA_7279:inst|key_7279_tmp[4] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279_tmp[3] ; |E-TRY|FPGA_7279:inst|key_7279_tmp[3] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279_tmp[2] ; |E-TRY|FPGA_7279:inst|key_7279_tmp[2] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279_tmp[1] ; |E-TRY|FPGA_7279:inst|key_7279_tmp[1] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279_tmp[0] ; |E-TRY|FPGA_7279:inst|key_7279_tmp[0] ; regout ;
; |E-TRY|FPGA_7279:inst|Select~1061 ; |E-TRY|FPGA_7279:inst|Select~1061 ; combout ;
; |E-TRY|rtl~44 ; |E-TRY|rtl~44 ; combout ;
; |E-TRY|rtl~44 ; |E-TRY|FPGA_7279:inst|cmd_tmp1[2] ; regout ;
; |E-TRY|FPGA_7279:inst|process0~0 ; |E-TRY|FPGA_7279:inst|process0~0 ; combout ;
; |E-TRY|FPGA_7279:inst|Select~1066 ; |E-TRY|FPGA_7279:inst|Select~1066 ; combout ;
; |E-TRY|FPGA_7279:inst|Select~1066 ; |E-TRY|FPGA_7279:inst|state.shift_data_high ; regout ;
; |E-TRY|FPGA_7279:inst|Select~1067 ; |E-TRY|FPGA_7279:inst|Select~1067 ; combout ;
; |E-TRY|FPGA_7279:inst|cmd_tmp[2] ; |E-TRY|FPGA_7279:inst|cmd_tmp[2] ; regout ;
; |E-TRY|FPGA_7279:inst|cmd_tmp[0] ; |E-TRY|FPGA_7279:inst|cmd_tmp[0] ; regout ;
; |E-TRY|FPGA_7279:inst|cmd_tmp[1] ; |E-TRY|FPGA_7279:inst|cmd_tmp[1] ; regout ;
; |E-TRY|rtl~45 ; |E-TRY|rtl~45 ; combout ;
; |E-TRY|rtl~45 ; |E-TRY|FPGA_7279:inst|cmd_tmp[7] ; regout ;
; |E-TRY|FPGA_7279:inst|Select~1068 ; |E-TRY|FPGA_7279:inst|Select~1068 ; combout ;
; |E-TRY|FPGA_7279:inst|Select~1068 ; |E-TRY|FPGA_7279:inst|state.shift_key_high1 ; regout ;
; |E-TRY|FPGA_7279:inst|Decoder~106 ; |E-TRY|FPGA_7279:inst|Decoder~106 ; combout ;
; |E-TRY|FPGA_7279:inst|Decoder~106 ; |E-TRY|FPGA_7279:inst|state.shift_key_high ; regout ;
; |E-TRY|FPGA_7279:inst|Decoder~107 ; |E-TRY|FPGA_7279:inst|Decoder~107 ; combout ;
; |E-TRY|FPGA_7279:inst|sdata_cnt[2]~426 ; |E-TRY|FPGA_7279:inst|sdata_cnt[2]~426 ; combout ;
; |E-TRY|FPGA_7279:inst|Decoder~108 ; |E-TRY|FPGA_7279:inst|Decoder~108 ; combout ;
; |E-TRY|FPGA_7279:inst|Decoder~109 ; |E-TRY|FPGA_7279:inst|Decoder~109 ; combout ;
; |E-TRY|FPGA_7279:inst|Decoder~110 ; |E-TRY|FPGA_7279:inst|Decoder~110 ; combout ;
; |E-TRY|FPGA_7279:inst|Decoder~111 ; |E-TRY|FPGA_7279:inst|Decoder~111 ; combout ;
; |E-TRY|FPGA_7279:inst|Decoder~112 ; |E-TRY|FPGA_7279:inst|Decoder~112 ; combout ;
; |E-TRY|FPGA_7279:inst|Decoder~113 ; |E-TRY|FPGA_7279:inst|Decoder~113 ; combout ;
; |E-TRY|FPGA_7279:inst|Decoder~114 ; |E-TRY|FPGA_7279:inst|Decoder~114 ; combout ;
; |E-TRY|FPGA_7279:inst|process0~1 ; |E-TRY|FPGA_7279:inst|process0~1 ; regout ;
; |E-TRY|FPGA_7279:inst|data_start ; |E-TRY|FPGA_7279:inst|data_start ; regout ;
; |E-TRY|FPGA_7279:inst|seg_cnt[2] ; |E-TRY|FPGA_7279:inst|seg_cnt[2] ; regout ;
; |E-TRY|FPGA_7279:inst|seg_cnt[0] ; |E-TRY|FPGA_7279:inst|seg_cnt[0] ; regout ;
; |E-TRY|FPGA_7279:inst|seg_cnt[1] ; |E-TRY|FPGA_7279:inst|seg_cnt[1] ; regout ;
; |E-TRY|FPGA_7279:inst|Select~1075 ; |E-TRY|FPGA_7279:inst|cmd_tmp1[0] ; regout ;
; |E-TRY|FPGA_7279:inst|Select~1081 ; |E-TRY|FPGA_7279:inst|cmd_tmp1[1] ; regout ;
; |E-TRY|FPGA_7279:inst|Select~1082 ; |E-TRY|FPGA_7279:inst|cmd_tmp1[7] ; regout ;
; |E-TRY|SYS_RST_N ; |E-TRY|SYS_RST_N ; combout ;
; |E-TRY|KEY7279 ; |E-TRY|KEY7279 ; combout ;
; |E-TRY|CS_8019 ; |E-TRY|CS_8019 ; padio ;
; |E-TRY|KEY_EN ; |E-TRY|KEY_EN ; padio ;
; |E-TRY|start1 ; |E-TRY|start1 ; padio ;
; |E-TRY|aa ; |E-TRY|aa ; padio ;
; |E-TRY|ena ; |E-TRY|ena ; padio ;
; |E-TRY|OUT7279[7] ; |E-TRY|OUT7279[7] ; padio ;
; |E-TRY|OUT7279[6] ; |E-TRY|OUT7279[6] ; padio ;
; |E-TRY|OUT7279[5] ; |E-TRY|OUT7279[5] ; padio ;
; |E-TRY|OUT7279[4] ; |E-TRY|OUT7279[4] ; padio ;
; |E-TRY|OUT7279[3] ; |E-TRY|OUT7279[3] ; padio ;
; |E-TRY|OUT7279[2] ; |E-TRY|OUT7279[2] ; padio ;
; |E-TRY|OUT7279[1] ; |E-TRY|OUT7279[1] ; padio ;
; |E-TRY|OUT7279[0] ; |E-TRY|OUT7279[0] ; padio ;
; |E-TRY|DAT7279~0 ; |E-TRY|DAT7279~0 ; combout ;
+--------------------------------------------+---------------------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Fri May 23 22:42:47 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off E-TRY -c E-TRY
Warning: Can't display state machine states -- register holding state machine bit "|E-TRY|etester:inst8|state.wr_stop" was synthesized away
Warning: Can't display state machine states -- register holding state machine bit "|E-TRY|etester:inst8|state.d_hold" was synthesized away
Warning: Can't display state machine states -- register holding state machine bit "|E-TRY|etester:inst8|state.d_write" was synthesized away
Warning: Can't display state machine states -- register holding state machine bit "|E-TRY|etester:inst8|state.d_setup1" was synthesized away
Warning: Can't display state machine states -- register holding state machine bit "|E-TRY|etester:inst8|state.d_setup" was synthesized away
Warning: Can't display state machine states -- register holding state machine bit "|E-TRY|etester:inst8|state.start" was synthesized away
Warning: Can't display state machine states -- register holding state machine bit "|E-TRY|etester:inst8|state.idle" was synthesized away
Warning: Can't display state machine states -- register holding state machine bit "|E-TRY|FPGA_7279:inst|state1.stop" was synthesized away
Warning: Can't display state machine states -- register holding state machine bit "|E-TRY|FPGA_7279:inst|state1.start_wr" was synthesized away
Warning: Can't display state machine states -- register holding state machine bit "|E-TRY|FPGA_7279:inst|state1.idle" was synthesized away
Warning: Ignored node in vector source file. Can't find corresponding node name "AD_INT" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "FLASH_D[7]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "FLASH_D[6]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "FLASH_D[5]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "FLASH_D[4]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "FLASH_D[3]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "FLASH_D[2]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "FLASH_D[1]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "FLASH_D[0]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "AD_RD" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "AD_WR" in design.
Warning: Compiler packed, optimized or synthesized away node "FLASH_A[2]". Ignored vector source file node.
Warning: Compiler packed, optimized or synthesized away node "FLASH_A[1]". Ignored vector source file node.
Warning: Compiler packed, optimized or synthesized away node "FLASH_A[0]". Ignored vector source file node.
Warning: Can't find signal in vector source file for input pin "|E-TRY|tclk"
Warning: Can't find signal in vector source file for input pin "|E-TRY|KEY7279"
Warning: Can't find signal in vector source file for input pin "|E-TRY|DAT7279"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Warning: Found logic contention at time 32.02 us on bus node "|E-TRY|DAT7279"
Info: Node "DAT7279~output" has logic level of 0
Info: Node "DAT7279" has logic level of X
Warning: Found logic contention at time 48.02 us on bus node "|E-TRY|DAT7279"
Info: Node "DAT7279~output" has logic level of 1
Info: Node "DAT7279" has logic level of X
Warning: Found logic contention at time 56.02 us on bus node "|E-TRY|DAT7279"
Info: Node "DAT7279~output" has logic level of 0
Info: Node "DAT7279" has logic level of X
Warning: Found logic contention at time 72.02 us on bus node "|E-TRY|DAT7279"
Info: Node "DAT7279~output" has logic level of 0
Info: Node "DAT7279" has logic level of X
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 43.78 %
Info: Number of transitions in simulation is 24278725
Info: Quartus II Simulator was successful. 0 errors, 31 warnings
Info: Processing ended: Fri May 23 22:52:06 2008
Info: Elapsed time: 00:09:20
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