📄 e-try.sim.rpt
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; |E-TRY|div:inst7|LessThan~596 ; |E-TRY|div:inst7|LessThan~596 ; combout ;
; |E-TRY|FPGA_7279:inst|scmd_cnt[0] ; |E-TRY|FPGA_7279:inst|scmd_cnt[0] ; regout ;
; |E-TRY|FPGA_7279:inst|Select~1062 ; |E-TRY|FPGA_7279:inst|Select~1062 ; combout ;
; |E-TRY|FPGA_7279:inst|delay_cnt[1] ; |E-TRY|FPGA_7279:inst|delay_cnt[1] ; regout ;
; |E-TRY|FPGA_7279:inst|Select~1064 ; |E-TRY|FPGA_7279:inst|Select~1064 ; combout ;
; |E-TRY|FPGA_7279:inst|LessThan~112 ; |E-TRY|FPGA_7279:inst|LessThan~112 ; combout ;
; |E-TRY|FPGA_7279:inst|Select~1065 ; |E-TRY|FPGA_7279:inst|Select~1065 ; combout ;
; |E-TRY|FPGA_7279:inst|Select~1065 ; |E-TRY|FPGA_7279:inst|state.shift_cmd_low ; regout ;
; |E-TRY|FPGA_7279:inst|DAT7279~reg0 ; |E-TRY|FPGA_7279:inst|DAT7279~reg0 ; regout ;
; |E-TRY|FPGA_7279:inst|scmd_cnt[2]~333 ; |E-TRY|FPGA_7279:inst|scmd_cnt[2]~333 ; combout ;
; |E-TRY|FPGA_7279:inst|data_start_tmp~0 ; |E-TRY|FPGA_7279:inst|data_start_tmp~0 ; combout ;
; |E-TRY|FPGA_7279:inst|delay_cnt[0] ; |E-TRY|FPGA_7279:inst|delay_cnt[0] ; regout ;
; |E-TRY|FPGA_7279:inst|reduce_or~52 ; |E-TRY|FPGA_7279:inst|reduce_or~52 ; combout ;
; |E-TRY|FPGA_7279:inst|reduce_or~52 ; |E-TRY|FPGA_7279:inst|state.shift_cmd_high ; regout ;
; |E-TRY|FPGA_7279:inst|delay_cnt[1]~779 ; |E-TRY|FPGA_7279:inst|delay_cnt[1]~779 ; combout ;
; |E-TRY|FPGA_7279:inst|delay_cnt[1]~780 ; |E-TRY|FPGA_7279:inst|delay_cnt[1]~780 ; combout ;
; |E-TRY|FPGA_7279:inst|delay_cnt[1]~781 ; |E-TRY|FPGA_7279:inst|delay_cnt[1]~781 ; combout ;
; |E-TRY|FPGA_7279:inst|reduce_or~53 ; |E-TRY|FPGA_7279:inst|reduce_or~53 ; combout ;
; |E-TRY|FPGA_7279:inst|cmd_tmp[7]~46 ; |E-TRY|FPGA_7279:inst|cmd_tmp[7]~46 ; combout ;
; |E-TRY|FPGA_7279:inst|Select~1077 ; |E-TRY|FPGA_7279:inst|Select~1077 ; combout ;
; |E-TRY|FPGA_7279:inst|Select~1081 ; |E-TRY|FPGA_7279:inst|Select~1081 ; combout ;
; |E-TRY|FPGA_7279:inst|Select~1082 ; |E-TRY|FPGA_7279:inst|Select~1082 ; combout ;
; |E-TRY|SYS_CLK ; |E-TRY|SYS_CLK ; combout ;
; |E-TRY|CLK7279 ; |E-TRY|CLK7279 ; padio ;
; |E-TRY|AD_CLK500K ; |E-TRY|AD_CLK500K ; padio ;
; |E-TRY|CLK16us ; |E-TRY|CLK16us ; padio ;
; |E-TRY|DAT7279~0 ; |E-TRY|DAT7279~output ; padio ;
+----------------------------------------+--------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+--------------------------------------------+---------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+--------------------------------------------+---------------------------------------------+------------------+
; |E-TRY|FPGA_7279:inst|key_7279[7] ; |E-TRY|FPGA_7279:inst|key_7279[7] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279[6] ; |E-TRY|FPGA_7279:inst|key_7279[6] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279[5] ; |E-TRY|FPGA_7279:inst|key_7279[5] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279[4] ; |E-TRY|FPGA_7279:inst|key_7279[4] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279[3] ; |E-TRY|FPGA_7279:inst|key_7279[3] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279[2] ; |E-TRY|FPGA_7279:inst|key_7279[2] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279[1] ; |E-TRY|FPGA_7279:inst|key_7279[1] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279[0] ; |E-TRY|FPGA_7279:inst|key_7279[0] ; regout ;
; |E-TRY|FPGA_7279:inst|state.finish ; |E-TRY|FPGA_7279:inst|state.finish ; regout ;
; |E-TRY|FPGA_7279:inst|state.shift_data_low ; |E-TRY|FPGA_7279:inst|state.shift_data_low ; regout ;
; |E-TRY|FPGA_7279:inst|state.shift_key_low ; |E-TRY|FPGA_7279:inst|state.shift_key_low ; regout ;
; |E-TRY|FPGA_7279:inst|state.next_delay ; |E-TRY|FPGA_7279:inst|state.next_delay ; regout ;
; |E-TRY|div:inst6|fre_N[4] ; |E-TRY|div:inst6|fre_N[4]~141COUT1_151 ; cout1 ;
; |E-TRY|div:inst1|fre_N[5] ; |E-TRY|div:inst1|fre_N[5]~140 ; cout0 ;
; |E-TRY|div:inst1|fre_N[6] ; |E-TRY|div:inst1|fre_N[6]~144 ; cout0 ;
; |E-TRY|div:inst7|fre_N[23] ; |E-TRY|div:inst7|fre_N[23]~380 ; cout0 ;
; |E-TRY|div:inst7|fre_N[23] ; |E-TRY|div:inst7|fre_N[23]~380COUT1_498 ; cout1 ;
; |E-TRY|div:inst7|fre_N[17] ; |E-TRY|div:inst7|fre_N[17]~384 ; cout0 ;
; |E-TRY|div:inst7|fre_N[18] ; |E-TRY|div:inst7|fre_N[18]~392 ; cout0 ;
; |E-TRY|div:inst7|fre_N[19] ; |E-TRY|div:inst7|fre_N[19]~396 ; cout0 ;
; |E-TRY|div:inst7|fre_N[15] ; |E-TRY|div:inst7|fre_N[15]~404COUT1_492 ; cout1 ;
; |E-TRY|div:inst7|fre_N[20] ; |E-TRY|div:inst7|fre_N[20]~408 ; cout0 ;
; |E-TRY|div:inst7|fre_N[20] ; |E-TRY|div:inst7|fre_N[20]~408COUT1_496 ; cout1 ;
; |E-TRY|div:inst7|fre_N[21] ; |E-TRY|div:inst7|fre_N[21]~412 ; cout ;
; |E-TRY|div:inst7|fre_N[22] ; |E-TRY|div:inst7|fre_N[22]~416 ; cout0 ;
; |E-TRY|div:inst7|fre_N[22] ; |E-TRY|div:inst7|fre_N[22]~416COUT1_497 ; cout1 ;
; |E-TRY|div:inst7|LessThan~591 ; |E-TRY|div:inst7|LessThan~591 ; combout ;
; |E-TRY|div:inst7|fre_N[2] ; |E-TRY|div:inst7|fre_N[2]~428COUT1_481 ; cout1 ;
; |E-TRY|div:inst7|fre_N[3] ; |E-TRY|div:inst7|fre_N[3]~432COUT1_482 ; cout1 ;
; |E-TRY|div:inst7|fre_N[4] ; |E-TRY|div:inst7|fre_N[4]~436COUT1_483 ; cout1 ;
; |E-TRY|div:inst7|fre_N[5] ; |E-TRY|div:inst7|fre_N[5]~440COUT1_484 ; cout1 ;
; |E-TRY|div:inst7|fre_N[7] ; |E-TRY|div:inst7|fre_N[7]~444 ; cout0 ;
; |E-TRY|div:inst7|fre_N[8] ; |E-TRY|div:inst7|fre_N[8]~448 ; cout0 ;
; |E-TRY|div:inst7|fre_N[9] ; |E-TRY|div:inst7|fre_N[9]~452 ; cout0 ;
; |E-TRY|div:inst7|fre_N[10] ; |E-TRY|div:inst7|fre_N[10]~456 ; cout0 ;
; |E-TRY|div:inst7|fre_N[12] ; |E-TRY|div:inst7|fre_N[12]~468COUT1_489 ; cout1 ;
; |E-TRY|div:inst7|fre_N[13] ; |E-TRY|div:inst7|fre_N[13]~472COUT1_490 ; cout1 ;
; |E-TRY|div:inst7|fre_N[14] ; |E-TRY|div:inst7|fre_N[14]~476COUT1_491 ; cout1 ;
; |E-TRY|div:inst7|LessThan~597 ; |E-TRY|div:inst7|LessThan~597 ; combout ;
; |E-TRY|div:inst7|LessThan~598 ; |E-TRY|div:inst7|LessThan~598 ; combout ;
; |E-TRY|FPGA_7279:inst|key_7279_tmp[7] ; |E-TRY|FPGA_7279:inst|key_7279_tmp[7] ; regout ;
; |E-TRY|FPGA_7279:inst|sdata_cnt[0] ; |E-TRY|FPGA_7279:inst|sdata_cnt[0] ; regout ;
; |E-TRY|FPGA_7279:inst|LessThan~111 ; |E-TRY|FPGA_7279:inst|LessThan~111 ; combout ;
; |E-TRY|FPGA_7279:inst|key_7279[7]~54 ; |E-TRY|FPGA_7279:inst|key_7279[7]~54 ; combout ;
; |E-TRY|FPGA_7279:inst|key_7279_tmp[6] ; |E-TRY|FPGA_7279:inst|key_7279_tmp[6] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279_tmp[5] ; |E-TRY|FPGA_7279:inst|key_7279_tmp[5] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279_tmp[4] ; |E-TRY|FPGA_7279:inst|key_7279_tmp[4] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279_tmp[3] ; |E-TRY|FPGA_7279:inst|key_7279_tmp[3] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279_tmp[2] ; |E-TRY|FPGA_7279:inst|key_7279_tmp[2] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279_tmp[1] ; |E-TRY|FPGA_7279:inst|key_7279_tmp[1] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279_tmp[0] ; |E-TRY|FPGA_7279:inst|key_7279_tmp[0] ; regout ;
; |E-TRY|FPGA_7279:inst|Select~1061 ; |E-TRY|FPGA_7279:inst|Select~1061 ; combout ;
; |E-TRY|rtl~44 ; |E-TRY|rtl~44 ; combout ;
; |E-TRY|rtl~44 ; |E-TRY|FPGA_7279:inst|cmd_tmp1[2] ; regout ;
; |E-TRY|FPGA_7279:inst|process0~0 ; |E-TRY|FPGA_7279:inst|process0~0 ; combout ;
; |E-TRY|FPGA_7279:inst|Select~1066 ; |E-TRY|FPGA_7279:inst|Select~1066 ; combout ;
; |E-TRY|FPGA_7279:inst|Select~1066 ; |E-TRY|FPGA_7279:inst|state.shift_data_high ; regout ;
; |E-TRY|FPGA_7279:inst|Select~1067 ; |E-TRY|FPGA_7279:inst|Select~1067 ; combout ;
; |E-TRY|FPGA_7279:inst|cmd_tmp[2] ; |E-TRY|FPGA_7279:inst|cmd_tmp[2] ; regout ;
; |E-TRY|FPGA_7279:inst|cmd_tmp[0] ; |E-TRY|FPGA_7279:inst|cmd_tmp[0] ; regout ;
; |E-TRY|FPGA_7279:inst|cmd_tmp[1] ; |E-TRY|FPGA_7279:inst|cmd_tmp[1] ; regout ;
; |E-TRY|rtl~45 ; |E-TRY|rtl~45 ; combout ;
; |E-TRY|rtl~45 ; |E-TRY|FPGA_7279:inst|cmd_tmp[7] ; regout ;
; |E-TRY|FPGA_7279:inst|Select~1068 ; |E-TRY|FPGA_7279:inst|Select~1068 ; combout ;
; |E-TRY|FPGA_7279:inst|Select~1068 ; |E-TRY|FPGA_7279:inst|state.shift_key_high1 ; regout ;
; |E-TRY|FPGA_7279:inst|Decoder~106 ; |E-TRY|FPGA_7279:inst|Decoder~106 ; combout ;
; |E-TRY|FPGA_7279:inst|Decoder~106 ; |E-TRY|FPGA_7279:inst|state.shift_key_high ; regout ;
; |E-TRY|FPGA_7279:inst|Decoder~107 ; |E-TRY|FPGA_7279:inst|Decoder~107 ; combout ;
; |E-TRY|FPGA_7279:inst|sdata_cnt[2]~426 ; |E-TRY|FPGA_7279:inst|sdata_cnt[2]~426 ; combout ;
; |E-TRY|FPGA_7279:inst|Decoder~108 ; |E-TRY|FPGA_7279:inst|Decoder~108 ; combout ;
; |E-TRY|FPGA_7279:inst|Decoder~109 ; |E-TRY|FPGA_7279:inst|Decoder~109 ; combout ;
; |E-TRY|FPGA_7279:inst|Decoder~110 ; |E-TRY|FPGA_7279:inst|Decoder~110 ; combout ;
; |E-TRY|FPGA_7279:inst|Decoder~111 ; |E-TRY|FPGA_7279:inst|Decoder~111 ; combout ;
; |E-TRY|FPGA_7279:inst|Decoder~112 ; |E-TRY|FPGA_7279:inst|Decoder~112 ; combout ;
; |E-TRY|FPGA_7279:inst|Decoder~113 ; |E-TRY|FPGA_7279:inst|Decoder~113 ; combout ;
; |E-TRY|FPGA_7279:inst|Decoder~114 ; |E-TRY|FPGA_7279:inst|Decoder~114 ; combout ;
; |E-TRY|FPGA_7279:inst|data_start ; |E-TRY|FPGA_7279:inst|data_start ; regout ;
; |E-TRY|FPGA_7279:inst|seg_cnt[2] ; |E-TRY|FPGA_7279:inst|seg_cnt[2] ; regout ;
; |E-TRY|FPGA_7279:inst|seg_cnt[0] ; |E-TRY|FPGA_7279:inst|seg_cnt[0] ; regout ;
; |E-TRY|FPGA_7279:inst|seg_cnt[1] ; |E-TRY|FPGA_7279:inst|seg_cnt[1] ; regout ;
; |E-TRY|FPGA_7279:inst|Select~1075 ; |E-TRY|FPGA_7279:inst|Select~1075 ; combout ;
; |E-TRY|FPGA_7279:inst|Select~1075 ; |E-TRY|FPGA_7279:inst|cmd_tmp1[0] ; regout ;
; |E-TRY|FPGA_7279:inst|seg_cnt[2]~3 ; |E-TRY|FPGA_7279:inst|seg_cnt[2]~3 ; combout ;
; |E-TRY|FPGA_7279:inst|Select~1081 ; |E-TRY|FPGA_7279:inst|cmd_tmp1[1] ; regout ;
; |E-TRY|FPGA_7279:inst|Select~1082 ; |E-TRY|FPGA_7279:inst|cmd_tmp1[7] ; regout ;
; |E-TRY|KEY7279 ; |E-TRY|KEY7279 ; combout ;
; |E-TRY|CS_8019 ; |E-TRY|CS_8019 ; padio ;
; |E-TRY|KEY_EN ; |E-TRY|KEY_EN ; padio ;
; |E-TRY|CS7279 ; |E-TRY|CS7279 ; padio ;
; |E-TRY|start1 ; |E-TRY|start1 ; padio ;
; |E-TRY|aa ; |E-TRY|aa ; padio ;
; |E-TRY|ena ; |E-TRY|ena ; padio ;
; |E-TRY|OUT7279[7] ; |E-TRY|OUT7279[7] ; padio ;
; |E-TRY|OUT7279[6] ; |E-TRY|OUT7279[6] ; padio ;
; |E-TRY|OUT7279[5] ; |E-TRY|OUT7279[5] ; padio ;
; |E-TRY|OUT7279[4] ; |E-TRY|OUT7279[4] ; padio ;
; |E-TRY|OUT7279[3] ; |E-TRY|OUT7279[3] ; padio ;
; |E-TRY|OUT7279[2] ; |E-TRY|OUT7279[2] ; padio ;
; |E-TRY|OUT7279[1] ; |E-TRY|OUT7279[1] ; padio ;
; |E-TRY|OUT7279[0] ; |E-TRY|OUT7279[0] ; padio ;
; |E-TRY|DAT7279~0 ; |E-TRY|DAT7279~0 ; combout ;
+--------------------------------------------+---------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+-------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+--------------------------------------------+---------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+--------------------------------------------+---------------------------------------------+------------------+
; |E-TRY|FPGA_7279:inst|key_7279[7] ; |E-TRY|FPGA_7279:inst|key_7279[7] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279[6] ; |E-TRY|FPGA_7279:inst|key_7279[6] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279[5] ; |E-TRY|FPGA_7279:inst|key_7279[5] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279[4] ; |E-TRY|FPGA_7279:inst|key_7279[4] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279[3] ; |E-TRY|FPGA_7279:inst|key_7279[3] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279[2] ; |E-TRY|FPGA_7279:inst|key_7279[2] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279[1] ; |E-TRY|FPGA_7279:inst|key_7279[1] ; regout ;
; |E-TRY|FPGA_7279:inst|key_7279[0] ; |E-TRY|FPGA_7279:inst|key_7279[0] ; regout ;
; |E-TRY|FPGA_7279:inst|state.shift_data_low ; |E-TRY|FPGA_7279:inst|state.shift_data_low ; regout ;
; |E-TRY|FPGA_7279:inst|state.shift_key_low ; |E-TRY|FPGA_7279:inst|state.shift_key_low ; regout ;
; |E-TRY|FPGA_7279:inst|state.next_delay ; |E-TRY|FPGA_7279:inst|state.next_delay ; regout ;
; |E-TRY|FPGA_7279:inst|state.idle ; |E-TRY|FPGA_7279:inst|state.idle ; regout ;
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