e-try.map.rpt

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+----------------+----------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: div:inst1 ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type                          ;
+----------------+-------+-------------------------------+
; div_nx2        ; 200   ; Untyped                       ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: div:inst6 ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type                          ;
+----------------+-------+-------------------------------+
; div_nx2        ; 50    ; Untyped                       ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/Users/wear/Desktop/E-TRY(frequency)/E-TRY.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Sat May 24 10:18:12 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off E-TRY -c E-TRY
Info: Found 2 design units, including 1 entities, in source file DIV.vhd
    Info: Found design unit 1: div-behav
    Info: Found entity 1: div
Info: Found 2 design units, including 1 entities, in source file FPGA_7279.vhd
    Info: Found design unit 1: FPGA_7279-behav
    Info: Found entity 1: FPGA_7279
Info: Found 1 design units, including 1 entities, in source file E-TRY.bdf
    Info: Found entity 1: E-TRY
Info: Found 2 design units, including 1 entities, in source file Test_Controller.vhd
    Info: Found design unit 1: Test_Controller-behav
    Info: Found entity 1: Test_Controller
Info: Found 2 design units, including 1 entities, in source file bcdzhuanhuan.vhd
    Info: Found design unit 1: BCD-A
    Info: Found entity 1: BCD
Info: Found 2 design units, including 1 entities, in source file etester.vhd
    Info: Found design unit 1: etester-behav
    Info: Found entity 1: etester
Info: Found 2 design units, including 1 entities, in source file DIV5000.vhd
    Info: Found design unit 1: DIV2500-behav
    Info: Found entity 1: DIV2500
Info: Elaborating entity "E-TRY" for the top level hierarchy
Warning: Block or symbol "etester" of instance "inst8" overlaps another block or symbol
Warning: Port "tclk" of type etester and instance "inst8" is missing source signal
Warning: Port "RDKY_EN" of type etester and instance "inst8" is missing source signal
Warning: Port "ena" of type etester and instance "inst8" is missing source signal
Warning: Port "D_KEY" of type etester and instance "inst8" is missing source signal
Warning: Pin "tclk" not connected
Info: Elaborating entity "FPGA_7279" for hierarchy "FPGA_7279:inst"
Info (10035): Verilog HDL or VHDL information at FPGA_7279.vhd(47): object "cmd_7279" declared but not used
Info (10035): Verilog HDL or VHDL information at FPGA_7279.vhd(59): object "f_edge_cnt" declared but not used
Warning (10036): Verilog HDL or VHDL warning at FPGA_7279.vhd(64): object "cmd_start_tmp" assigned a value but never read
Info (10035): Verilog HDL or VHDL information at FPGA_7279.vhd(68): object "seg_r" declared but not used
Info (10425): VHDL Case Statement information at FPGA_7279.vhd(188): OTHERS choice is never selected
Warning (10492): VHDL Process Statement warning at FPGA_7279.vhd(226): signal "RD_N" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info (10425): VHDL Case Statement information at FPGA_7279.vhd(276): OTHERS choice is never selected
Info: Elaborating entity "etester" for hierarchy "etester:inst8"
Warning (10036): Verilog HDL or VHDL warning at etester.vhd(35): object "dp" assigned a value but never read
Info (10035): Verilog HDL or VHDL information at etester.vhd(36): object "seg_cnt" declared but not used
Info (10035): Verilog HDL or VHDL information at etester.vhd(37): object "seg1_cnt" declared but not used
Info (10035): Verilog HDL or VHDL information at etester.vhd(41): object "state_ky" declared but not used
Info (10035): Verilog HDL or VHDL information at etester.vhd(55): object "data_tmp" declared but not used
Info (10035): Verilog HDL or VHDL information at etester.vhd(57): object "present_state" declared but not used
Info (10035): Verilog HDL or VHDL information at etester.vhd(57): object "next_state" declared but not used
Warning (10036): Verilog HDL or VHDL warning at etester.vhd(60): object "bdata" assigned a value but never read
Warning (10541): VHDL Signal Declaration warning at etester.vhd(65): used implicit default value for signal "bena" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Warning (10631): VHDL Process Statement warning at etester.vhd(106): signal or variable "bzq" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "bzq" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10034): Output port "RD_N" at etester.vhd(26) has no driver
Warning (10034): Output port "A_BUS[2]" at etester.vhd(28) has no driver
Warning (10034): Output port "A_BUS[1]" at etester.vhd(28) has no driver
Warning (10034): Output port "A_BUS[0]" at etester.vhd(28) has no driver
Info: Elaborating entity "div" for hierarchy "div:inst7"
Info: Elaborating entity "div" for hierarchy "div:inst1"
Info: Elaborating entity "div" for hierarchy "div:inst6"
Warning: No clock transition on "etester:inst8|tsq[31]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[31]" with stuck clock port to stuck value GND
Warning: No clock transition on "etester:inst8|tsq[30]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[30]" with stuck clock port to stuck value GND
Warning: No clock transition on "etester:inst8|tsq[29]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[29]" with stuck clock port to stuck value GND
Warning: No clock transition on "etester:inst8|tsq[28]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[28]" with stuck clock port to stuck value GND
Warning: No clock transition on "etester:inst8|tsq[27]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[27]" with stuck clock port to stuck value GND
Warning: No clock transition on "etester:inst8|tsq[26]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[26]" with stuck clock port to stuck value GND
Warning: No clock transition on "etester:inst8|tsq[25]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[25]" with stuck clock port to stuck value GND
Warning: No clock transition on "etester:inst8|tsq[24]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[24]" with stuck clock port to stuck value GND
Warning: No clock transition on "etester:inst8|tsq[23]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[23]" with stuck clock port to stuck value GND
Warning: No clock transition on "etester:inst8|tsq[22]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[22]" with stuck clock port to stuck value GND
Warning: No clock transition on "etester:inst8|tsq[21]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[21]" with stuck clock port to stuck value GND
Warning: No clock transition on "etester:inst8|tsq[20]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[20]" with stuck clock port to stuck value GND
Warning: No clock transition on "etester:inst8|tsq[19]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[19]" with stuck clock port to stuck value GND
Warning: No clock transition on "etester:inst8|tsq[18]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[18]" with stuck clock port to stuck value GND
Warning: No clock transition on "etester:inst8|tsq[17]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[17]" with stuck clock port to stuck value GND
Warning: No clock transition on "etester:inst8|tsq[16]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[16]" with stuck clock port to stuck value GND
Warning: No clock transition on "etester:inst8|tsq[15]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[15]" with stuck clock port to stuck value GND
Warning: No clock transition on "etester:inst8|tsq[14]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[14]" with stuck clock port to stuck value GND
Warning: No clock transition on "etester:inst8|tsq[13]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[13]" with stuck clock port to stuck value GND
Warning: No clock transition on "etester:inst8|tsq[12]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[12]" with stuck clock port to stuck value GND
Warning: No clock transition on "etester:inst8|tsq[11]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[11]" with stuck clock port to stuck value GND
Warning: No clock transition on "etester:inst8|tsq[10]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[10]" with stuck clock port to stuck value GND
Warning: No clock transition on "etester:inst8|tsq[9]" register due to stuck clock or clock enable
Warning: Reduced register "etester:inst8|tsq[9]" with stuck clock port to stuck value GND