e-try.tan.qmsg

频率计编程 看看吧第一次先贴希望对大家有用

{ "Info" "ITDB_TH_RESULT" "FPGA_7279:inst\|seg_cnt\[0\] SYS_RST_N SYS_CLK 6.985 ns register " "Info: th for register \"FPGA_7279:inst\|seg_cnt\[0\]\" (data pin = \"SYS_RST_N\", clock pin = \"SYS_CLK\") is 6.985 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK destination 9.972 ns + Longest register " "Info: + Longest clock path from clock \"SYS_CLK\" to destination register is 9.972 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYS_CLK 1 CLK PIN_153 42 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 42; CLK Node = 'SYS_CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "" { SYS_CLK } "NODE_NAME" } "" } } { "E-TRY.bdf" "" { Schematic "C:/Users/wear/Desktop/E-TRY(frequency)/E-TRY.bdf" { { 88 64 232 104 "SYS_CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.935 ns) 3.469 ns div:inst1\|clk_tmp 2 REG LC_X25_Y16_N2 55 " "Info: 2: + IC(1.065 ns) + CELL(0.935 ns) = 3.469 ns; Loc. = LC_X25_Y16_N2; Fanout = 55; REG Node = 'div:inst1\|clk_tmp'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "2.000 ns" { SYS_CLK div:inst1|clk_tmp } "NODE_NAME" } "" } } { "DIV.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/DIV.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.792 ns) + CELL(0.711 ns) 9.972 ns FPGA_7279:inst\|seg_cnt\[0\] 3 REG LC_X43_Y18_N5 4 " "Info: 3: + IC(5.792 ns) + CELL(0.711 ns) = 9.972 ns; Loc. = LC_X43_Y18_N5; Fanout = 4; REG Node = 'FPGA_7279:inst\|seg_cnt\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "6.503 ns" { div:inst1|clk_tmp FPGA_7279:inst|seg_cnt[0] } "NODE_NAME" } "" } } { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 31.24 % ) " "Info: Total cell delay = 3.115 ns ( 31.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.857 ns ( 68.76 % ) " "Info: Total interconnect delay = 6.857 ns ( 68.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "9.972 ns" { SYS_CLK div:inst1|clk_tmp FPGA_7279:inst|seg_cnt[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.972 ns" { SYS_CLK SYS_CLK~out0 div:inst1|clk_tmp FPGA_7279:inst|seg_cnt[0] } { 0.000ns 0.000ns 1.065ns 5.792ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.002 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.002 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYS_RST_N 1 PIN PIN_131 75 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_131; Fanout = 75; PIN Node = 'SYS_RST_N'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "" { SYS_RST_N } "NODE_NAME" } "" } } { "E-TRY.bdf" "" { Schematic "C:/Users/wear/Desktop/E-TRY(frequency)/E-TRY.bdf" { { 104 64 232 120 "SYS_RST_N" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.224 ns) + CELL(0.309 ns) 3.002 ns FPGA_7279:inst\|seg_cnt\[0\] 2 REG LC_X43_Y18_N5 4 " "Info: 2: + IC(1.224 ns) + CELL(0.309 ns) = 3.002 ns; Loc. = LC_X43_Y18_N5; Fanout = 4; REG Node = 'FPGA_7279:inst\|seg_cnt\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "1.533 ns" { SYS_RST_N FPGA_7279:inst|seg_cnt[0] } "NODE_NAME" } "" } } { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns ( 59.23 % ) " "Info: Total cell delay = 1.778 ns ( 59.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.224 ns ( 40.77 % ) " "Info: Total interconnect delay = 1.224 ns ( 40.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "3.002 ns" { SYS_RST_N FPGA_7279:inst|seg_cnt[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.002 ns" { SYS_RST_N SYS_RST_N~out0 FPGA_7279:inst|seg_cnt[0] } { 0.000ns 0.000ns 1.224ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "9.972 ns" { SYS_CLK div:inst1|clk_tmp FPGA_7279:inst|seg_cnt[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.972 ns" { SYS_CLK SYS_CLK~out0 div:inst1|clk_tmp FPGA_7279:inst|seg_cnt[0] } { 0.000ns 0.000ns 1.065ns 5.792ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "3.002 ns" { SYS_RST_N FPGA_7279:inst|seg_cnt[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.002 ns" { SYS_RST_N SYS_RST_N~out0 FPGA_7279:inst|seg_cnt[0] } { 0.000ns 0.000ns 1.224ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 24 10:18:40 2008 " "Info: Processing ended: Sat May 24 10:18:40 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}