e-try.tan.qmsg

频率计编程 看看吧第一次先贴希望对大家有用

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "div:inst1\|clk_tmp " "Info: Detected ripple clock \"div:inst1\|clk_tmp\" as buffer" {  } { { "DIV.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/DIV.vhd" 23 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "div:inst1\|clk_tmp" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SYS_CLK register div:inst7\|fre_N\[8\] register div:inst7\|clk_tmp 114.67 MHz 8.721 ns Internal " "Info: Clock \"SYS_CLK\" has Internal fmax of 114.67 MHz between source register \"div:inst7\|fre_N\[8\]\" and destination register \"div:inst7\|clk_tmp\" (period= 8.721 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.361 ns + Longest register register " "Info: + Longest register to register delay is 8.361 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div:inst7\|fre_N\[8\] 1 REG LC_X12_Y13_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y13_N1; Fanout = 4; REG Node = 'div:inst7\|fre_N\[8\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "" { div:inst7|fre_N[8] } "NODE_NAME" } "" } } { "DIV.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/DIV.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.580 ns) + CELL(0.292 ns) 1.872 ns div:inst7\|LessThan~594 2 COMB LC_X11_Y14_N2 1 " "Info: 2: + IC(1.580 ns) + CELL(0.292 ns) = 1.872 ns; Loc. = LC_X11_Y14_N2; Fanout = 1; COMB Node = 'div:inst7\|LessThan~594'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "1.872 ns" { div:inst7|fre_N[8] div:inst7|LessThan~594 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.670 ns) + CELL(0.442 ns) 2.984 ns div:inst7\|LessThan~596 3 COMB LC_X12_Y14_N2 1 " "Info: 3: + IC(0.670 ns) + CELL(0.442 ns) = 2.984 ns; Loc. = LC_X12_Y14_N2; Fanout = 1; COMB Node = 'div:inst7\|LessThan~596'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "1.112 ns" { div:inst7|LessThan~594 div:inst7|LessThan~596 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.218 ns) + CELL(0.590 ns) 4.792 ns div:inst7\|LessThan~597 4 COMB LC_X12_Y12_N8 1 " "Info: 4: + IC(1.218 ns) + CELL(0.590 ns) = 4.792 ns; Loc. = LC_X12_Y12_N8; Fanout = 1; COMB Node = 'div:inst7\|LessThan~597'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "1.808 ns" { div:inst7|LessThan~596 div:inst7|LessThan~597 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.412 ns) + CELL(0.442 ns) 5.646 ns div:inst7\|LessThan~598 5 COMB LC_X12_Y12_N9 26 " "Info: 5: + IC(0.412 ns) + CELL(0.442 ns) = 5.646 ns; Loc. = LC_X12_Y12_N9; Fanout = 26; COMB Node = 'div:inst7\|LessThan~598'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "0.854 ns" { div:inst7|LessThan~597 div:inst7|LessThan~598 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.237 ns) + CELL(0.478 ns) 8.361 ns div:inst7\|clk_tmp 6 REG LC_X28_Y12_N2 2 " "Info: 6: + IC(2.237 ns) + CELL(0.478 ns) = 8.361 ns; Loc. = LC_X28_Y12_N2; Fanout = 2; REG Node = 'div:inst7\|clk_tmp'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "2.715 ns" { div:inst7|LessThan~598 div:inst7|clk_tmp } "NODE_NAME" } "" } } { "DIV.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/DIV.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.244 ns ( 26.84 % ) " "Info: Total cell delay = 2.244 ns ( 26.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.117 ns ( 73.16 % ) " "Info: Total interconnect delay = 6.117 ns ( 73.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "8.361 ns" { div:inst7|fre_N[8] div:inst7|LessThan~594 div:inst7|LessThan~596 div:inst7|LessThan~597 div:inst7|LessThan~598 div:inst7|clk_tmp } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.361 ns" { div:inst7|fre_N[8] div:inst7|LessThan~594 div:inst7|LessThan~596 div:inst7|LessThan~597 div:inst7|LessThan~598 div:inst7|clk_tmp } { 0.000ns 1.580ns 0.670ns 1.218ns 0.412ns 2.237ns } { 0.000ns 0.292ns 0.442ns 0.590ns 0.442ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.099 ns - Smallest " "Info: - Smallest clock skew is -0.099 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK destination 3.111 ns + Shortest register " "Info: + Shortest clock path from clock \"SYS_CLK\" to destination register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYS_CLK 1 CLK PIN_153 42 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 42; CLK Node = 'SYS_CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "" { SYS_CLK } "NODE_NAME" } "" } } { "E-TRY.bdf" "" { Schematic "C:/Users/wear/Desktop/E-TRY(frequency)/E-TRY.bdf" { { 88 64 232 104 "SYS_CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns div:inst7\|clk_tmp 2 REG LC_X28_Y12_N2 2 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X28_Y12_N2; Fanout = 2; REG Node = 'div:inst7\|clk_tmp'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "1.642 ns" { SYS_CLK div:inst7|clk_tmp } "NODE_NAME" } "" } } { "DIV.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/DIV.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 70.07 % ) " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns ( 29.93 % ) " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "3.111 ns" { SYS_CLK div:inst7|clk_tmp } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.111 ns" { SYS_CLK SYS_CLK~out0 div:inst7|clk_tmp } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK source 3.210 ns - Longest register " "Info: - Longest clock path from clock \"SYS_CLK\" to source register is 3.210 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYS_CLK 1 CLK PIN_153 42 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 42; CLK Node = 'SYS_CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "" { SYS_CLK } "NODE_NAME" } "" } } { "E-TRY.bdf" "" { Schematic "C:/Users/wear/Desktop/E-TRY(frequency)/E-TRY.bdf" { { 88 64 232 104 "SYS_CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.711 ns) 3.210 ns div:inst7\|fre_N\[8\] 2 REG LC_X12_Y13_N1 4 " "Info: 2: + IC(1.030 ns) + CELL(0.711 ns) = 3.210 ns; Loc. = LC_X12_Y13_N1; Fanout = 4; REG Node = 'div:inst7\|fre_N\[8\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "1.741 ns" { SYS_CLK div:inst7|fre_N[8] } "NODE_NAME" } "" } } { "DIV.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/DIV.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.91 % ) " "Info: Total cell delay = 2.180 ns ( 67.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.030 ns ( 32.09 % ) " "Info: Total interconnect delay = 1.030 ns ( 32.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "3.210 ns" { SYS_CLK div:inst7|fre_N[8] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.210 ns" { SYS_CLK SYS_CLK~out0 div:inst7|fre_N[8] } { 0.000ns 0.000ns 1.030ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "3.111 ns" { SYS_CLK div:inst7|clk_tmp } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.111 ns" { SYS_CLK SYS_CLK~out0 div:inst7|clk_tmp } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "3.210 ns" { SYS_CLK div:inst7|fre_N[8] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.210 ns" { SYS_CLK SYS_CLK~out0 div:inst7|fre_N[8] } { 0.000ns 0.000ns 1.030ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "DIV.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/DIV.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "DIV.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/DIV.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "8.361 ns" { div:inst7|fre_N[8] div:inst7|LessThan~594 div:inst7|LessThan~596 div:inst7|LessThan~597 div:inst7|LessThan~598 div:inst7|clk_tmp } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.361 ns" { div:inst7|fre_N[8] div:inst7|LessThan~594 div:inst7|LessThan~596 div:inst7|LessThan~597 div:inst7|LessThan~598 div:inst7|clk_tmp } { 0.000ns 1.580ns 0.670ns 1.218ns 0.412ns 2.237ns } { 0.000ns 0.292ns 0.442ns 0.590ns 0.442ns 0.478ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "3.111 ns" { SYS_CLK div:inst7|clk_tmp } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.111 ns" { SYS_CLK SYS_CLK~out0 div:inst7|clk_tmp } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "3.210 ns" { SYS_CLK div:inst7|fre_N[8] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.210 ns" { SYS_CLK SYS_CLK~out0 div:inst7|fre_N[8] } { 0.000ns 0.000ns 1.030ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "FPGA_7279:inst\|key_7279\[0\] KEY7279 SYS_CLK 0.796 ns register " "Info: tsu for register \"FPGA_7279:inst\|key_7279\[0\]\" (data pin = \"KEY7279\", clock pin = \"SYS_CLK\") is 0.796 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.731 ns + Longest pin register " "Info: + Longest pin to register delay is 10.731 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns KEY7279 1 PIN PIN_159 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_159; Fanout = 9; PIN Node = 'KEY7279'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "" { KEY7279 } "NODE_NAME" } "" } } { "E-TRY.bdf" "" { Schematic "C:/Users/wear/Desktop/E-TRY(frequency)/E-TRY.bdf" { { 616 48 216 632 "KEY7279" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.853 ns) + CELL(0.292 ns) 8.614 ns FPGA_7279:inst\|key_7279\[7\]~54 2 COMB LC_X42_Y17_N3 8 " "Info: 2: + IC(6.853 ns) + CELL(0.292 ns) = 8.614 ns; Loc. = LC_X42_Y17_N3; Fanout = 8; COMB Node = 'FPGA_7279:inst\|key_7279\[7\]~54'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "7.145 ns" { KEY7279 FPGA_7279:inst|key_7279[7]~54 } "NODE_NAME" } "" } } { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.250 ns) + CELL(0.867 ns) 10.731 ns FPGA_7279:inst\|key_7279\[0\] 3 REG LC_X42_Y18_N6 1 " "Info: 3: + IC(1.250 ns) + CELL(0.867 ns) = 10.731 ns; Loc. = LC_X42_Y18_N6; Fanout = 1; REG Node = 'FPGA_7279:inst\|key_7279\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "2.117 ns" { FPGA_7279:inst|key_7279[7]~54 FPGA_7279:inst|key_7279[0] } "NODE_NAME" } "" } } { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.628 ns ( 24.49 % ) " "Info: Total cell delay = 2.628 ns ( 24.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.103 ns ( 75.51 % ) " "Info: Total interconnect delay = 8.103 ns ( 75.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "10.731 ns" { KEY7279 FPGA_7279:inst|key_7279[7]~54 FPGA_7279:inst|key_7279[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.731 ns" { KEY7279 KEY7279~out0 FPGA_7279:inst|key_7279[7]~54 FPGA_7279:inst|key_7279[0] } { 0.000ns 0.000ns 6.853ns 1.250ns } { 0.000ns 1.469ns 0.292ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK destination 9.972 ns - Shortest register " "Info: - Shortest clock path from clock \"SYS_CLK\" to destination register is 9.972 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYS_CLK 1 CLK PIN_153 42 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 42; CLK Node = 'SYS_CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "" { SYS_CLK } "NODE_NAME" } "" } } { "E-TRY.bdf" "" { Schematic "C:/Users/wear/Desktop/E-TRY(frequency)/E-TRY.bdf" { { 88 64 232 104 "SYS_CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.935 ns) 3.469 ns div:inst1\|clk_tmp 2 REG LC_X25_Y16_N2 55 " "Info: 2: + IC(1.065 ns) + CELL(0.935 ns) = 3.469 ns; Loc. = LC_X25_Y16_N2; Fanout = 55; REG Node = 'div:inst1\|clk_tmp'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "2.000 ns" { SYS_CLK div:inst1|clk_tmp } "NODE_NAME" } "" } } { "DIV.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/DIV.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.792 ns) + CELL(0.711 ns) 9.972 ns FPGA_7279:inst\|key_7279\[0\] 3 REG LC_X42_Y18_N6 1 " "Info: 3: + IC(5.792 ns) + CELL(0.711 ns) = 9.972 ns; Loc. = LC_X42_Y18_N6; Fanout = 1; REG Node = 'FPGA_7279:inst\|key_7279\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "6.503 ns" { div:inst1|clk_tmp FPGA_7279:inst|key_7279[0] } "NODE_NAME" } "" } } { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 31.24 % ) " "Info: Total cell delay = 3.115 ns ( 31.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.857 ns ( 68.76 % ) " "Info: Total interconnect delay = 6.857 ns ( 68.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "9.972 ns" { SYS_CLK div:inst1|clk_tmp FPGA_7279:inst|key_7279[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.972 ns" { SYS_CLK SYS_CLK~out0 div:inst1|clk_tmp FPGA_7279:inst|key_7279[0] } { 0.000ns 0.000ns 1.065ns 5.792ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "10.731 ns" { KEY7279 FPGA_7279:inst|key_7279[7]~54 FPGA_7279:inst|key_7279[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.731 ns" { KEY7279 KEY7279~out0 FPGA_7279:inst|key_7279[7]~54 FPGA_7279:inst|key_7279[0] } { 0.000ns 0.000ns 6.853ns 1.250ns } { 0.000ns 1.469ns 0.292ns 0.867ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "9.972 ns" { SYS_CLK div:inst1|clk_tmp FPGA_7279:inst|key_7279[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.972 ns" { SYS_CLK SYS_CLK~out0 div:inst1|clk_tmp FPGA_7279:inst|key_7279[0] } { 0.000ns 0.000ns 1.065ns 5.792ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "SYS_CLK CS7279 FPGA_7279:inst\|CS7279 16.159 ns register " "Info: tco from clock \"SYS_CLK\" to destination pin \"CS7279\" through register \"FPGA_7279:inst\|CS7279\" is 16.159 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK source 9.972 ns + Longest register " "Info: + Longest clock path from clock \"SYS_CLK\" to source register is 9.972 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYS_CLK 1 CLK PIN_153 42 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 42; CLK Node = 'SYS_CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "" { SYS_CLK } "NODE_NAME" } "" } } { "E-TRY.bdf" "" { Schematic "C:/Users/wear/Desktop/E-TRY(frequency)/E-TRY.bdf" { { 88 64 232 104 "SYS_CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.935 ns) 3.469 ns div:inst1\|clk_tmp 2 REG LC_X25_Y16_N2 55 " "Info: 2: + IC(1.065 ns) + CELL(0.935 ns) = 3.469 ns; Loc. = LC_X25_Y16_N2; Fanout = 55; REG Node = 'div:inst1\|clk_tmp'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "2.000 ns" { SYS_CLK div:inst1|clk_tmp } "NODE_NAME" } "" } } { "DIV.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/DIV.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.792 ns) + CELL(0.711 ns) 9.972 ns FPGA_7279:inst\|CS7279 3 REG LC_X43_Y18_N3 2 " "Info: 3: + IC(5.792 ns) + CELL(0.711 ns) = 9.972 ns; Loc. = LC_X43_Y18_N3; Fanout = 2; REG Node = 'FPGA_7279:inst\|CS7279'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "6.503 ns" { div:inst1|clk_tmp FPGA_7279:inst|CS7279 } "NODE_NAME" } "" } } { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 31.24 % ) " "Info: Total cell delay = 3.115 ns ( 31.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.857 ns ( 68.76 % ) " "Info: Total interconnect delay = 6.857 ns ( 68.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "9.972 ns" { SYS_CLK div:inst1|clk_tmp FPGA_7279:inst|CS7279 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.972 ns" { SYS_CLK SYS_CLK~out0 div:inst1|clk_tmp FPGA_7279:inst|CS7279 } { 0.000ns 0.000ns 1.065ns 5.792ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.963 ns + Longest register pin " "Info: + Longest register to pin delay is 5.963 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FPGA_7279:inst\|CS7279 1 REG LC_X43_Y18_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X43_Y18_N3; Fanout = 2; REG Node = 'FPGA_7279:inst\|CS7279'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "" { FPGA_7279:inst|CS7279 } "NODE_NAME" } "" } } { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.839 ns) + CELL(2.124 ns) 5.963 ns CS7279 2 PIN PIN_132 0 " "Info: 2: + IC(3.839 ns) + CELL(2.124 ns) = 5.963 ns; Loc. = PIN_132; Fanout = 0; PIN Node = 'CS7279'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "5.963 ns" { FPGA_7279:inst|CS7279 CS7279 } "NODE_NAME" } "" } } { "E-TRY.bdf" "" { Schematic "C:/Users/wear/Desktop/E-TRY(frequency)/E-TRY.bdf" { { 368 784 960 384 "CS7279" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 35.62 % ) " "Info: Total cell delay = 2.124 ns ( 35.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.839 ns ( 64.38 % ) " "Info: Total interconnect delay = 3.839 ns ( 64.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "5.963 ns" { FPGA_7279:inst|CS7279 CS7279 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.963 ns" { FPGA_7279:inst|CS7279 CS7279 } { 0.000ns 3.839ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "9.972 ns" { SYS_CLK div:inst1|clk_tmp FPGA_7279:inst|CS7279 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.972 ns" { SYS_CLK SYS_CLK~out0 div:inst1|clk_tmp FPGA_7279:inst|CS7279 } { 0.000ns 0.000ns 1.065ns 5.792ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "E-TRY" "UNKNOWN" "V1" "C:/Users/wear/Desktop/E-TRY(frequency)/db/E-TRY.quartus_db" { Floorplan "C:/Users/wear/Desktop/E-TRY(frequency)/" "" "5.963 ns" { FPGA_7279:inst|CS7279 CS7279 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.963 ns" { FPGA_7279:inst|CS7279 CS7279 } { 0.000ns 3.839ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}