e-try.fit.qmsg

频率计编程 看看吧第一次先贴希望对大家有用

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "SYS_RST_N Global clock in PIN 131 " "Info: Automatically promoted some destinations of signal \"SYS_RST_N\" to use Global clock in PIN 131" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "div:inst6\|clk_tmp " "Info: Destination \"div:inst6\|clk_tmp\" may be non-global or may not use global clock" {  } { { "DIV.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/DIV.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "div:inst1\|clk_tmp " "Info: Destination \"div:inst1\|clk_tmp\" may be non-global or may not use global clock" {  } { { "DIV.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/DIV.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "div:inst7\|clk_tmp " "Info: Destination \"div:inst7\|clk_tmp\" may be non-global or may not use global clock" {  } { { "DIV.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/DIV.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FPGA_7279:inst\|Decoder~106 " "Info: Destination \"FPGA_7279:inst\|Decoder~106\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FPGA_7279:inst\|sdata_cnt\[2\]~426 " "Info: Destination \"FPGA_7279:inst\|sdata_cnt\[2\]~426\" may be non-global or may not use global clock" {  } { { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FPGA_7279:inst\|scmd_cnt\[2\]~333 " "Info: Destination \"FPGA_7279:inst\|scmd_cnt\[2\]~333\" may be non-global or may not use global clock" {  } { { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FPGA_7279:inst\|data_start_tmp~0 " "Info: Destination \"FPGA_7279:inst\|data_start_tmp~0\" may be non-global or may not use global clock" {  } { { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 65 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FPGA_7279:inst\|delay_cnt\[1\]~779 " "Info: Destination \"FPGA_7279:inst\|delay_cnt\[1\]~779\" may be non-global or may not use global clock" {  } { { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FPGA_7279:inst\|cmd_tmp\[7\]~46 " "Info: Destination \"FPGA_7279:inst\|cmd_tmp\[7\]~46\" may be non-global or may not use global clock" {  } { { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FPGA_7279:inst\|seg_cnt\[0\] " "Info: Destination \"FPGA_7279:inst\|seg_cnt\[0\]\" may be non-global or may not use global clock" {  } { { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0 0 "Limited to %1!d! non-global destinations" 0 0}  } { { "E-TRY.bdf" "" { Schematic "C:/Users/wear/Desktop/E-TRY(frequency)/E-TRY.bdf" { { 104 64 232 120 "SYS_RST_N" "" } } } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0 0 "Started Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0 0 "Finished Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "6 unused 3.30 0 6 0 " "Info: Number of I/O pins in group: 6 (unused VREF, 3.30 VCCIO, 0 input, 6 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 2 42 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  42 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 42 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.30V 11 34 " "Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 11 total pin(s) used --  34 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.30V 5 37 " "Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 5 total pin(s) used --  37 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLK20us1 " "Warning: Node \"CLK20us1\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK20us1" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FLASH_A\[0\] " "Warning: Node \"FLASH_A\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "FLASH_A\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FLASH_A\[1\] " "Warning: Node \"FLASH_A\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "FLASH_A\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FLASH_A\[2\] " "Warning: Node \"FLASH_A\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "FLASH_A\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SYS_CLOCK " "Warning: Node \"SYS_CLOCK\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SYS_CLOCK" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SYS_RESET_N " "Warning: Node \"SYS_RESET_N\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SYS_RESET_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0}  } {  } 0 0 "Ignored locations or region assignments to the following nodes" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}