e-try.map.qmsg

来自「频率计编程 看看吧第一次先贴希望对大家有用」· QMSG 代码 · 共 170 行 · 第 1/5 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 24 10:18:12 2008 " "Info: Processing started: Sat May 24 10:18:12 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off E-TRY -c E-TRY " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off E-TRY -c E-TRY" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DIV.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DIV.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div-behav " "Info: Found design unit 1: div-behav" {  } { { "DIV.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/DIV.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 div " "Info: Found entity 1: div" {  } { { "DIV.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/DIV.vhd" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FPGA_7279.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file FPGA_7279.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FPGA_7279-behav " "Info: Found design unit 1: FPGA_7279-behav" {  } { { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 30 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 FPGA_7279 " "Info: Found entity 1: FPGA_7279" {  } { { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "E-TRY.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file E-TRY.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 E-TRY " "Info: Found entity 1: E-TRY" {  } { { "E-TRY.bdf" "" { Schematic "C:/Users/wear/Desktop/E-TRY(frequency)/E-TRY.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Test_Controller.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Test_Controller.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Test_Controller-behav " "Info: Found design unit 1: Test_Controller-behav" {  } { { "Test_Controller.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/Test_Controller.vhd" 29 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Test_Controller " "Info: Found entity 1: Test_Controller" {  } { { "Test_Controller.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/Test_Controller.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bcdzhuanhuan.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file bcdzhuanhuan.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 BCD-A " "Info: Found design unit 1: BCD-A" {  } { { "bcdzhuanhuan.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/bcdzhuanhuan.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 BCD " "Info: Found entity 1: BCD" {  } { { "bcdzhuanhuan.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/bcdzhuanhuan.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "etester.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file etester.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 etester-behav " "Info: Found design unit 1: etester-behav" {  } { { "etester.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/etester.vhd" 34 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 etester " "Info: Found entity 1: etester" {  } { { "etester.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/etester.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DIV5000.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DIV5000.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DIV2500-behav " "Info: Found design unit 1: DIV2500-behav" {  } { { "DIV5000.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/DIV5000.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 DIV2500 " "Info: Found entity 1: DIV2500" {  } { { "DIV5000.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/DIV5000.vhd" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "E-TRY " "Info: Elaborating entity \"E-TRY\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "etester inst8 " "Warning: Block or symbol \"etester\" of instance \"inst8\" overlaps another block or symbol" {  } { { "E-TRY.bdf" "" { Schematic "C:/Users/wear/Desktop/E-TRY(frequency)/E-TRY.bdf" { { 328 304 480 488 "inst8" "" } } } }  } 0 0 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "tclk etester inst8 " "Warning: Port \"tclk\" of type etester and instance \"inst8\" is missing source signal" {  } { { "E-TRY.bdf" "" { Schematic "C:/Users/wear/Desktop/E-TRY(frequency)/E-TRY.bdf" { { 328 304 480 488 "inst8" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "RDKY_EN etester inst8 " "Warning: Port \"RDKY_EN\" of type etester and instance \"inst8\" is missing source signal" {  } { { "E-TRY.bdf" "" { Schematic "C:/Users/wear/Desktop/E-TRY(frequency)/E-TRY.bdf" { { 328 304 480 488 "inst8" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "ena etester inst8 " "Warning: Port \"ena\" of type etester and instance \"inst8\" is missing source signal" {  } { { "E-TRY.bdf" "" { Schematic "C:/Users/wear/Desktop/E-TRY(frequency)/E-TRY.bdf" { { 328 304 480 488 "inst8" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D_KEY etester inst8 " "Warning: Port \"D_KEY\" of type etester and instance \"inst8\" is missing source signal" {  } { { "E-TRY.bdf" "" { Schematic "C:/Users/wear/Desktop/E-TRY(frequency)/E-TRY.bdf" { { 328 304 480 488 "inst8" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_PIN_IGNORED" "tclk " "Warning: Pin \"tclk\" not connected" {  } { { "E-TRY.bdf" "" { Schematic "C:/Users/wear/Desktop/E-TRY(frequency)/E-TRY.bdf" { { 384 144 312 400 "tclk" "" } } } }  } 0 0 "Pin \"%1!s!\" not connected" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FPGA_7279 FPGA_7279:inst " "Info: Elaborating entity \"FPGA_7279\" for hierarchy \"FPGA_7279:inst\"" {  } { { "E-TRY.bdf" "inst" { Schematic "C:/Users/wear/Desktop/E-TRY(frequency)/E-TRY.bdf" { { 312 544 728 488 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cmd_7279 FPGA_7279.vhd(47) " "Info (10035): Verilog HDL or VHDL information at FPGA_7279.vhd(47): object \"cmd_7279\" declared but not used" {  } { { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 47 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "f_edge_cnt FPGA_7279.vhd(59) " "Info (10035): Verilog HDL or VHDL information at FPGA_7279.vhd(59): object \"f_edge_cnt\" declared but not used" {  } { { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 59 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "cmd_start_tmp FPGA_7279.vhd(64) " "Warning (10036): Verilog HDL or VHDL warning at FPGA_7279.vhd(64): object \"cmd_start_tmp\" assigned a value but never read" {  } { { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 64 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "seg_r FPGA_7279.vhd(68) " "Info (10035): Verilog HDL or VHDL information at FPGA_7279.vhd(68): object \"seg_r\" declared but not used" {  } { { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 68 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "FPGA_7279.vhd(188) " "Info (10425): VHDL Case Statement information at FPGA_7279.vhd(188): OTHERS choice is never selected" {  } { { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 188 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "RD_N FPGA_7279.vhd(226) " "Warning (10492): VHDL Process Statement warning at FPGA_7279.vhd(226): signal \"RD_N\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 226 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "FPGA_7279.vhd(276) " "Info (10425): VHDL Case Statement information at FPGA_7279.vhd(276): OTHERS choice is never selected" {  } { { "FPGA_7279.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/FPGA_7279.vhd" 276 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "etester etester:inst8 " "Info: Elaborating entity \"etester\" for hierarchy \"etester:inst8\"" {  } { { "E-TRY.bdf" "inst8" { Schematic "C:/Users/wear/Desktop/E-TRY(frequency)/E-TRY.bdf" { { 328 304 480 488 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "dp etester.vhd(35) " "Warning (10036): Verilog HDL or VHDL warning at etester.vhd(35): object \"dp\" assigned a value but never read" {  } { { "etester.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/etester.vhd" 35 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "seg_cnt etester.vhd(36) " "Info (10035): Verilog HDL or VHDL information at etester.vhd(36): object \"seg_cnt\" declared but not used" {  } { { "etester.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/etester.vhd" 36 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "seg1_cnt etester.vhd(37) " "Info (10035): Verilog HDL or VHDL information at etester.vhd(37): object \"seg1_cnt\" declared but not used" {  } { { "etester.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/etester.vhd" 37 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "state_ky etester.vhd(41) " "Info (10035): Verilog HDL or VHDL information at etester.vhd(41): object \"state_ky\" declared but not used" {  } { { "etester.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/etester.vhd" 41 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "data_tmp etester.vhd(55) " "Info (10035): Verilog HDL or VHDL information at etester.vhd(55): object \"data_tmp\" declared but not used" {  } { { "etester.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/etester.vhd" 55 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "present_state etester.vhd(57) " "Info (10035): Verilog HDL or VHDL information at etester.vhd(57): object \"present_state\" declared but not used" {  } { { "etester.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/etester.vhd" 57 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "next_state etester.vhd(57) " "Info (10035): Verilog HDL or VHDL information at etester.vhd(57): object \"next_state\" declared but not used" {  } { { "etester.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/etester.vhd" 57 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "bdata etester.vhd(60) " "Warning (10036): Verilog HDL or VHDL warning at etester.vhd(60): object \"bdata\" assigned a value but never read" {  } { { "etester.vhd" "" { Text "C:/Users/wear/Desktop/E-TRY(frequency)/etester.vhd" 60 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}