test_controller.vhd

频率计编程 看看吧第一次先贴希望对大家有用

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_ARITH.all;
use IEEE.std_logic_UNSIGNED.all;

entity Test_Controller is
	port (
		--以下是引脚信号
		
		CLK       :IN	STD_LOGIC;  --系统时钟
		RST_N     :IN	STD_LOGIC;  --系统复位
		--AD0809部分接口
		AD_INT    :IN	STD_LOGIC;	--中断信号,转换完毕即中断,电平中断
		AD_CS     :OUT	STD_LOGIC;	--片选信号
		AD_RD     :OUT	STD_LOGIC;	--写信号
		AD_WR     :OUT	STD_LOGIC;	--读信号
		AD_A	  :OUT  STD_LOGIC_VECTOR(2 downto 0); --3位地址信号
		AD_D	  :IN   STD_LOGIC_VECTOR(7 downto 0); --8位数据
		--外部控制接口与本模块之间的信号		
		RDKY_EN   :IN     STD_LOGIC;  --存在有效键值, 高电平为存在有效键值, 外部接口读走数据后变低
		WR_N      :OUT    STD_LOGIC;  --外部写信号
		RD_N      :OUT    STD_LOGIC;  --外部读信号
		A_BUS	  :OUT  STD_LOGIC_VECTOR(2 downto 0);   --地址信号, 0为数据信号, 1为命令字
		D_BUS  	  :OUT  STD_LOGIC_VECTOR(7 downto 0);  --指令,数据输入及键盘值输出
		D_KEY  	  :IN   STD_LOGIC_VECTOR(7 downto 0)   --读键值
		);
end Test_Controller;

ARCHITECTURE behav OF Test_Controller IS
signal dp		: std_logic;	--小数点,1为显示
SIGNAL seg_cnt  : INTEGER RANGE 0 to 7;
SIGNAL seg1_cnt : INTEGER RANGE 0 to 7;
TYPE STATE_TYPE IS (IDLE, START, D_SETUP, D_SETUP1, D_WRITE, D_HOLD, WR_STOP);
	SIGNAL state: STATE_TYPE;
TYPE STATE_KEY IS (IDLE, START, STOP);
	SIGNAL state_ky: STATE_KEY;
TYPE SEG_Register IS ARRAY ( 0 To 7) of STD_LOGIC_VECTOR(7 DOWNTO 0);
	SIGNAL key_7279 :SEG_Register;
signal adin2,adin1,adin0 : std_logic_vector(3 downto 0);
SIGNAL a0,b2,b1,b0  : INTEGER RANGE 555555 downto 0;
signal datain : std_logic_vector(7 downto 0);
signal key0_7279 : std_logic_vector(7 downto 0);	--显示0位
signal key1_7279 : std_logic_vector(7 downto 0);	--显示1位
signal key2_7279 : std_logic_vector(7 downto 0);	--显示2位
signal key7_7279 : std_logic_vector(7 downto 0);	--显示7位
signal data_tmp : std_logic_vector(7 downto 0);
type statetype is(AD_IDLE, AD_ADDRESS, AD_WRITE, AD_WAIT, AD_READ, AD_STOP);
signal present_state,next_state: statetype;	

BEGIN

P1: process(present_state,next_state,AD_INT)
 begin
   case present_state is
     when AD_IDLE => 
		AD_CS <= '1'; 
		AD_WR <= '1'; 
		AD_RD <= '1';
        next_state <= AD_ADDRESS;
	 when AD_ADDRESS =>
		AD_A <= "000";	--使用AD0809的0通道
		AD_CS <= '0'; 
		next_state <= AD_WRITE;
     when AD_WRITE => 		
		AD_WR <= '0'; 
        next_state <= AD_WAIT;
     when AD_WAIT => 
		AD_CS <= '1'; 
		AD_WR <= '1'; 
        if (AD_INT = '0') then
          next_state <= AD_READ;
        else
          next_state <= AD_WAIT;
        end if;
     when AD_READ => 
		AD_CS <= '0'; 
		AD_RD <= '0';
        next_state <= AD_STOP;
	 when AD_STOP =>
		next_state <= AD_IDLE;
     end case;
end process P1;

P2: process(CLK, RST_N)
 begin
   if (RST_N = '0') then
     present_state <= AD_IDLE;
     datain <= "00000000";
   elsif falling_edge(CLK) then
     present_state <= next_state;
     if(present_state = AD_STOP) then
       datain <= AD_D;
     end if;
   end if;
end process P2;

process(CLK,RST_N)
	begin
	if (RST_N = '0') then
		for i in 0 to 7 loop
			key_7279(i) <= x"FF";
		end loop;
	elsif falling_edge(CLK) then
	a0<=conv_integer(datain);
		b2<=a0*2/100;
		b1<=(a0*2 mod 100)/10;
		b0<=a0*2 mod 10;
		adin0<=conv_std_logic_vector(b0,4);
		adin1<=conv_std_logic_vector(b1,4);
		adin2<=conv_std_logic_vector(b2,4);
		
		key_7279(0) <= "0000" & adin0(3 downto 0);
		key_7279(1) <= "0000" & adin1(3 downto 0);
		key_7279(2) <= "0000" & adin2(3 downto 0);
		--key_7279(7) <= "0000" & addr(3 downto 0);
	end if;
end process;

dp <= '0';	--不显示小数点
--写显示状态机
process(CLK,RST_N)
	begin
	if (RST_N = '0') then
		WR_N <= '1';
		D_BUS <= x"00";
		state <= IDLE;
		key0_7279 <= x"FF";
		key1_7279 <= x"FF";
		key2_7279 <= x"FF";
		key7_7279 <= x"FF";
	elsif falling_edge(CLK)	then
		case state is
			when IDLE =>				
				if (key0_7279 /= key_7279(0)) then	--当0位有新的显示值时,发送到7279
					WR_N <= '1';
					A_BUS <= "000";	--0位
					state <= START;
				elsif (key1_7279 /= key_7279(1)) then--当0位有新的显示值时,发送到7279
					WR_N <= '1';
					A_BUS <= "001";	--1位
					state <= START;
					elsif (key2_7279 /= key_7279(2)) then--当1位有新的显示值时,发送到7279
					WR_N <= '1';
					A_BUS <= "010";	--1位
					state <= START;
				elsif (key7_7279 /= key_7279(7)) then--当7位有新的显示值时,发送到7279
					WR_N <= '1';
					A_BUS <= "111";	--1位
					state <= START;
				end if;	
			when START =>
				if (key0_7279 /= key_7279(0)) then
					D_BUS <= dp & "000" & key_7279(0)(3 downto 0);
					key0_7279 <= key_7279(0);		 --更新0位显示值缓存
				elsif (key1_7279 /= key_7279(1)) then					
					D_BUS <= dp & "000" & key_7279(1)(3 downto 0);
					key1_7279 <= key_7279(1);		 --更新1位显示值缓存
					elsif (key2_7279 /= key_7279(2)) then					
					D_BUS <=  "1000" & key_7279(2)(3 downto 0);
					key2_7279 <= key_7279(2);	 --更新1位显示值缓存
				elsif (key7_7279 /= key_7279(7)) then					
					D_BUS <= dp & "000" & key_7279(7)(3 downto 0);
					key7_7279 <= key_7279(7);	
				end if;
				state <= D_SETUP;
			when D_SETUP =>		--两个时钟周期的建立时间
				WR_N <= '0';
				state <= D_SETUP1;
			when D_SETUP1 =>
				state <= D_HOLD;
			when D_HOLD =>		--保持时间
				WR_N <= '1';
				state <= WR_STOP;
			when WR_STOP =>	
				state <= IDLE;
			when others =>
				NULL;	
		end case;
	end if;
end process;

END behav;