div.vhd

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--Title	: 		Div (OCMJ2X8A LCD Controller)
--Corporation : BeiJing Techshine 
--Editor By: 	gxjao 
--Mail:			[e-mail]
--Data:	20080408
--Version:1.0
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div is
generic (div_nx2:positive:=50);
port (
		clr,clk:	in std_logic;
		q:	out std_logic);
end div ;
architecture behav of div is 
SIGNAL fre_N : integer range 0 to div_nx2;
SIGNAL clk_tmp: std_logic;
BEGIN
	q <= clk_tmp;
	process(clk,clr)
	begin
		if clr = '0' then
			fre_N <= 0;
		elsif falling_edge(clk) then
			if fre_N >= div_nx2 - 1 then
				fre_N <= 0;
				clk_tmp <= not clk_tmp;
			else
				fre_N <= fre_N + 1;
			end if;
		end if;
	end process;
end behav;