e-try.map.eqn

频率计编程 看看吧第一次先贴希望对大家有用

B1_data_start_tmp_lut_out = B1_data_start;
B1_data_start_tmp = DFFEAS(B1_data_start_tmp_lut_out, !C2_clk_tmp, VCC, , B1L17, , , , );


--B1_cmd_tmp1[2] is FPGA_7279:inst|cmd_tmp1[2]
--operation mode is normal

B1_cmd_tmp1[2]_lut_out = B1_cmd_tmp[2];
B1_cmd_tmp1[2] = DFFEAS(B1_cmd_tmp1[2]_lut_out, !C2_clk_tmp, VCC, , B1L17, , , , );


--B1_cmd_tmp1[7] is FPGA_7279:inst|cmd_tmp1[7]
--operation mode is normal

B1_cmd_tmp1[7]_lut_out = B1_cmd_tmp[7];
B1_cmd_tmp1[7] = DFFEAS(B1_cmd_tmp1[7]_lut_out, !C2_clk_tmp, VCC, , B1L17, , , , );


--A1L21 is rtl~44
--operation mode is normal

A1L21 = B1_cmd_tmp1[2] & (!B1_cmd_tmp1[7]);


--B1_cmd_tmp1[0] is FPGA_7279:inst|cmd_tmp1[0]
--operation mode is normal

B1_cmd_tmp1[0]_lut_out = B1_cmd_tmp[0];
B1_cmd_tmp1[0] = DFFEAS(B1_cmd_tmp1[0]_lut_out, !C2_clk_tmp, VCC, , B1L17, , , , );


--B1_cmd_tmp1[1] is FPGA_7279:inst|cmd_tmp1[1]
--operation mode is normal

B1_cmd_tmp1[1]_lut_out = B1_cmd_tmp[1];
B1_cmd_tmp1[1] = DFFEAS(B1_cmd_tmp1[1]_lut_out, !C2_clk_tmp, VCC, , B1L17, , , , );


--B1L54 is FPGA_7279:inst|process0~0
--operation mode is normal

B1L54 = B1_data_start_tmp # A1L21 & B1_cmd_tmp1[0] & !B1_cmd_tmp1[1];


--B1_delay_cnt[1] is FPGA_7279:inst|delay_cnt[1]
--operation mode is normal

B1_delay_cnt[1]_lut_out = B1L32 & (B1_delay_cnt[1] $ !B1_delay_cnt[0] # !B1L57) # !B1L32 & B1_delay_cnt[1];
B1_delay_cnt[1] = DFFEAS(B1_delay_cnt[1]_lut_out, !C2_clk_tmp, VCC, , , , , , );


--B1L77 is FPGA_7279:inst|Select~1064
--operation mode is normal

B1L77 = B1_state.start_delay & (!B1_delay_cnt[1]);


--B1L53 is FPGA_7279:inst|LessThan~112
--operation mode is normal

B1L53 = B1_scmd_cnt[1] # B1_scmd_cnt[0];


--B1L78 is FPGA_7279:inst|Select~1065
--operation mode is normal

B1L78 = B1L77 # B1_state.shift_cmd_high & (B1_scmd_cnt[2] # B1L53);


--B1L79 is FPGA_7279:inst|Select~1066
--operation mode is normal

B1L79 = B1_state.shift_data_high & (B1_sdata_cnt[2] # B1_sdata_cnt[1] # B1_sdata_cnt[0]);


--B1L80 is FPGA_7279:inst|Select~1067
--operation mode is normal

B1L80 = B1_state.next_delay & (!B1_delay_cnt[1]);


--B1_cmd_tmp[2] is FPGA_7279:inst|cmd_tmp[2]
--operation mode is normal

B1_cmd_tmp[2]_lut_out = B1_seg_cnt[2] # !KEY7279;
B1_cmd_tmp[2] = DFFEAS(B1_cmd_tmp[2]_lut_out, !C2_clk_tmp, VCC, , B1L12, , , , );


--B1_cmd_tmp[0] is FPGA_7279:inst|cmd_tmp[0]
--operation mode is normal

B1_cmd_tmp[0]_lut_out = B1_seg_cnt[0] # !KEY7279;
B1_cmd_tmp[0] = DFFEAS(B1_cmd_tmp[0]_lut_out, !C2_clk_tmp, VCC, , B1L12, , , , );


--B1_cmd_tmp[7] is FPGA_7279:inst|cmd_tmp[7]
--operation mode is normal

B1_cmd_tmp[7]_lut_out = KEY7279;
B1_cmd_tmp[7] = DFFEAS(B1_cmd_tmp[7]_lut_out, !C2_clk_tmp, VCC, , B1L12, , , , );


--B1_cmd_tmp[1] is FPGA_7279:inst|cmd_tmp[1]
--operation mode is normal

B1_cmd_tmp[1]_lut_out = KEY7279 & B1_seg_cnt[1];
B1_cmd_tmp[1] = DFFEAS(B1_cmd_tmp[1]_lut_out, !C2_clk_tmp, VCC, , B1L12, , , , );


--A1L22 is rtl~45
--operation mode is normal

A1L22 = B1_cmd_tmp[2] & B1_cmd_tmp[0] & !B1_cmd_tmp[7] & !B1_cmd_tmp[1];


--B1L81 is FPGA_7279:inst|Select~1068
--operation mode is normal

B1L81 = B1_state.shift_key_high1 & (B1_sdata_cnt[2] # B1_sdata_cnt[1] # B1_sdata_cnt[0]);


--B1L18 is FPGA_7279:inst|Decoder~106
--operation mode is normal

B1L18 = SYS_RST_N & B1_state.shift_key_high;


--B1L19 is FPGA_7279:inst|Decoder~107
--operation mode is normal

B1L19 = B1_sdata_cnt[0] & B1_sdata_cnt[1] & B1_sdata_cnt[2] & B1L18;


--B1L67 is FPGA_7279:inst|sdata_cnt[2]~426
--operation mode is normal

B1L67 = SYS_RST_N & (B1L79 # B1L80 # B1L81);


--B1L20 is FPGA_7279:inst|Decoder~108
--operation mode is normal

B1L20 = !B1_sdata_cnt[0] & B1_sdata_cnt[1] & B1_sdata_cnt[2] & B1L18;


--B1L21 is FPGA_7279:inst|Decoder~109
--operation mode is normal

B1L21 = B1_sdata_cnt[0] & !B1_sdata_cnt[1] & B1_sdata_cnt[2] & B1L18;


--B1L22 is FPGA_7279:inst|Decoder~110
--operation mode is normal

B1L22 = !B1_sdata_cnt[0] & !B1_sdata_cnt[1] & B1_sdata_cnt[2] & B1L18;


--B1L23 is FPGA_7279:inst|Decoder~111
--operation mode is normal

B1L23 = B1_sdata_cnt[0] & B1_sdata_cnt[1] & !B1_sdata_cnt[2] & B1L18;


--B1L24 is FPGA_7279:inst|Decoder~112
--operation mode is normal

B1L24 = !B1_sdata_cnt[0] & B1_sdata_cnt[1] & !B1_sdata_cnt[2] & B1L18;


--B1L25 is FPGA_7279:inst|Decoder~113
--operation mode is normal

B1L25 = B1_sdata_cnt[0] & !B1_sdata_cnt[1] & !B1_sdata_cnt[2] & B1L18;


--B1L26 is FPGA_7279:inst|Decoder~114
--operation mode is normal

B1L26 = !B1_sdata_cnt[0] & !B1_sdata_cnt[1] & !B1_sdata_cnt[2] & B1L18;


--B1L14Q is FPGA_7279:inst|DAT7279~reg0
--operation mode is normal

B1L14Q_lut_out = !B1_state.shift_data_low & (B1L85 # B1L82 & !B1_scmd_cnt[0]);
B1L14Q = DFFEAS(B1L14Q_lut_out, !C2_clk_tmp, SYS_RST_N, , B1L83, , , , );


--B1L55Q is FPGA_7279:inst|process0~1
--operation mode is normal

B1L55Q_lut_out = !B1_state.shift_key_low & (B1_state.idle);
B1L55Q = DFFEAS(B1L55Q_lut_out, !C2_clk_tmp, SYS_RST_N, , B1L83, , , , );


--B1L62 is FPGA_7279:inst|scmd_cnt[2]~333
--operation mode is normal

B1L62 = SYS_RST_N & B1L78;


--B1_data_start is FPGA_7279:inst|data_start
--operation mode is normal

B1_data_start_lut_out = B1_state.idle & B1_data_start # !B1_state.idle & (KEY7279);
B1_data_start = DFFEAS(B1_data_start_lut_out, !C2_clk_tmp, SYS_RST_N, , , , , , );


--B1L17 is FPGA_7279:inst|data_start_tmp~0
--operation mode is normal

B1L17 = B1_state.start & SYS_RST_N;


--B1_delay_cnt[0] is FPGA_7279:inst|delay_cnt[0]
--operation mode is normal

B1_delay_cnt[0]_lut_out = B1L32 & (B1_state.start # B1_state.shift_cmd_high # !B1_delay_cnt[0]) # !B1L32 & (B1_delay_cnt[0]);
B1_delay_cnt[0] = DFFEAS(B1_delay_cnt[0]_lut_out, !C2_clk_tmp, VCC, , , , , , );


--B1L56 is FPGA_7279:inst|reduce_or~52
--operation mode is normal

B1L56 = B1_state.start # B1_state.next_delay # B1_state.start_delay # B1_state.shift_cmd_high;


--B1L30 is FPGA_7279:inst|delay_cnt[1]~779
--operation mode is normal

B1L30 = SYS_RST_N & B1L56 & !B1L77 & !B1L80;


--B1L31 is FPGA_7279:inst|delay_cnt[1]~780
--operation mode is normal

B1L31 = !B1_scmd_cnt[2] & !B1_scmd_cnt[1] & !B1_scmd_cnt[0];


--B1L32 is FPGA_7279:inst|delay_cnt[1]~781
--operation mode is normal

B1L32 = B1L30 & (B1L54 & B1L31 # !B1_state.shift_cmd_high);


--B1L57 is FPGA_7279:inst|reduce_or~53
--operation mode is normal

B1L57 = !B1_state.start & !B1_state.shift_cmd_high;


--B1_seg_cnt[2] is FPGA_7279:inst|seg_cnt[2]
--operation mode is normal

B1_seg_cnt[2]_lut_out = B1_seg_cnt[2] $ (B1_seg_cnt[1] & B1_seg_cnt[0] & B1L72);
B1_seg_cnt[2] = DFFEAS(B1_seg_cnt[2]_lut_out, !C2_clk_tmp, VCC, , , , , , );


--B1L12 is FPGA_7279:inst|cmd_tmp[7]~46
--operation mode is normal

B1L12 = SYS_RST_N & (!B1_state.idle);


--B1_seg_cnt[0] is FPGA_7279:inst|seg_cnt[0]
--operation mode is normal

B1_seg_cnt[0]_lut_out = B1_seg_cnt[0] $ (!B1_state.idle & SYS_RST_N & KEY7279);
B1_seg_cnt[0] = DFFEAS(B1_seg_cnt[0]_lut_out, !C2_clk_tmp, VCC, , , , , , );


--B1_seg_cnt[1] is FPGA_7279:inst|seg_cnt[1]
--operation mode is normal

B1_seg_cnt[1]_lut_out = B1_seg_cnt[1] $ (B1_seg_cnt[0] & B1L72);
B1_seg_cnt[1] = DFFEAS(B1_seg_cnt[1]_lut_out, !C2_clk_tmp, VCC, , , , , , );


--B1L82 is FPGA_7279:inst|Select~1075
--operation mode is normal

B1L82 = !B1_scmd_cnt[2] & (B1_scmd_cnt[1] & B1_cmd_tmp1[2] # !B1_scmd_cnt[1] & (B1_cmd_tmp1[0]));


--B1L83 is FPGA_7279:inst|Select~1077
--operation mode is normal

B1L83 = B1_state.idle & (!B1L73) # !B1_state.idle & !KEY7279;


--B1L72 is FPGA_7279:inst|seg_cnt[2]~3
--operation mode is normal

B1L72 = SYS_RST_N & KEY7279 & (!B1_state.idle);


--B1L84 is FPGA_7279:inst|Select~1081
--operation mode is normal

B1L84 = B1_scmd_cnt[2] & (B1_scmd_cnt[1] $ !B1_scmd_cnt[0]) # !B1_scmd_cnt[2] & B1_cmd_tmp1[1] & !B1_scmd_cnt[1] & B1_scmd_cnt[0];


--B1L85 is FPGA_7279:inst|Select~1082
--operation mode is normal

B1L85 = B1L84 & (B1_cmd_tmp1[7] # !B1_scmd_cnt[1]);


--tclk is tclk
--operation mode is input

tclk = INPUT();


--SYS_RST_N is SYS_RST_N
--operation mode is input

SYS_RST_N = INPUT();


--SYS_CLK is SYS_CLK
--operation mode is input

SYS_CLK = INPUT();


--KEY7279 is KEY7279
--operation mode is input

KEY7279 = INPUT();


--CS_8019 is CS_8019
--operation mode is output

CS_8019 = OUTPUT(VCC);


--KEY_EN is KEY_EN
--operation mode is output

KEY_EN = OUTPUT(GND);


--CS7279 is CS7279
--operation mode is output

CS7279 = OUTPUT(!B1_CS7279);


--CLK7279 is CLK7279
--operation mode is output

CLK7279 = OUTPUT(B1_CLK7279);


--AD_CLK500K is AD_CLK500K
--operation mode is output

AD_CLK500K = OUTPUT(C3_clk_tmp);


--CLK16us is CLK16us
--operation mode is output

CLK16us = OUTPUT(C2_clk_tmp);


--start1 is start1
--operation mode is output

start1 = OUTPUT(GND);


--aa is aa
--operation mode is output

aa = OUTPUT(C1_clk_tmp);


--ena is ena
--operation mode is output

ena = OUTPUT(GND);


--OUT7279[7] is OUT7279[7]
--operation mode is output

OUT7279[7] = OUTPUT(B1_key_7279[7]);


--OUT7279[6] is OUT7279[6]
--operation mode is output

OUT7279[6] = OUTPUT(B1_key_7279[6]);


--OUT7279[5] is OUT7279[5]
--operation mode is output

OUT7279[5] = OUTPUT(B1_key_7279[5]);


--OUT7279[4] is OUT7279[4]
--operation mode is output

OUT7279[4] = OUTPUT(B1_key_7279[4]);


--OUT7279[3] is OUT7279[3]
--operation mode is output

OUT7279[3] = OUTPUT(B1_key_7279[3]);


--OUT7279[2] is OUT7279[2]
--operation mode is output

OUT7279[2] = OUTPUT(B1_key_7279[2]);


--OUT7279[1] is OUT7279[1]
--operation mode is output

OUT7279[1] = OUTPUT(B1_key_7279[1]);


--OUT7279[0] is OUT7279[0]
--operation mode is output

OUT7279[0] = OUTPUT(B1_key_7279[0]);


--A1L8 is DAT7279~0
--operation mode is bidir

A1L8 = DAT7279;

--DAT7279 is DAT7279
--operation mode is bidir

DAT7279_tri_out = TRI(B1L14Q, B1L55Q);
DAT7279 = BIDIR(DAT7279_tri_out);