e-try.map.eqn

频率计编程 看看吧第一次先贴希望对大家有用

--C1_fre_N[24] is div:inst7|fre_N[24]
--operation mode is normal

C1_fre_N[24]_carry_eqn = C1L50;
C1_fre_N[24]_lut_out = C1_fre_N[24] $ (!C1_fre_N[24]_carry_eqn);
C1_fre_N[24] = DFFEAS(C1_fre_N[24]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );


--C1_fre_N[15] is div:inst7|fre_N[15]
--operation mode is arithmetic

C1_fre_N[15]_carry_eqn = C1L32;
C1_fre_N[15]_lut_out = C1_fre_N[15] $ (C1_fre_N[15]_carry_eqn);
C1_fre_N[15] = DFFEAS(C1_fre_N[15]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L34 is div:inst7|fre_N[15]~404
--operation mode is arithmetic

C1L34 = CARRY(!C1L32 # !C1_fre_N[15]);


--C1_fre_N[20] is div:inst7|fre_N[20]
--operation mode is arithmetic

C1_fre_N[20]_carry_eqn = C1L42;
C1_fre_N[20]_lut_out = C1_fre_N[20] $ (!C1_fre_N[20]_carry_eqn);
C1_fre_N[20] = DFFEAS(C1_fre_N[20]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L44 is div:inst7|fre_N[20]~408
--operation mode is arithmetic

C1L44 = CARRY(C1_fre_N[20] & (!C1L42));


--C1_fre_N[21] is div:inst7|fre_N[21]
--operation mode is arithmetic

C1_fre_N[21]_carry_eqn = C1L44;
C1_fre_N[21]_lut_out = C1_fre_N[21] $ (C1_fre_N[21]_carry_eqn);
C1_fre_N[21] = DFFEAS(C1_fre_N[21]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L46 is div:inst7|fre_N[21]~412
--operation mode is arithmetic

C1L46 = CARRY(!C1L44 # !C1_fre_N[21]);


--C1_fre_N[22] is div:inst7|fre_N[22]
--operation mode is arithmetic

C1_fre_N[22]_carry_eqn = C1L46;
C1_fre_N[22]_lut_out = C1_fre_N[22] $ (!C1_fre_N[22]_carry_eqn);
C1_fre_N[22] = DFFEAS(C1_fre_N[22]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L48 is div:inst7|fre_N[22]~416
--operation mode is arithmetic

C1L48 = CARRY(C1_fre_N[22] & (!C1L46));


--C1L53 is div:inst7|LessThan~591
--operation mode is normal

C1L53 = !C1_fre_N[22] # !C1_fre_N[21] # !C1_fre_N[20];


--C1_fre_N[0] is div:inst7|fre_N[0]
--operation mode is arithmetic

C1_fre_N[0]_lut_out = !C1_fre_N[0];
C1_fre_N[0] = DFFEAS(C1_fre_N[0]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L4 is div:inst7|fre_N[0]~420
--operation mode is arithmetic

C1L4 = CARRY(C1_fre_N[0]);


--C1_fre_N[1] is div:inst7|fre_N[1]
--operation mode is arithmetic

C1_fre_N[1]_carry_eqn = C1L4;
C1_fre_N[1]_lut_out = C1_fre_N[1] $ (C1_fre_N[1]_carry_eqn);
C1_fre_N[1] = DFFEAS(C1_fre_N[1]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L6 is div:inst7|fre_N[1]~424
--operation mode is arithmetic

C1L6 = CARRY(!C1L4 # !C1_fre_N[1]);


--C1_fre_N[2] is div:inst7|fre_N[2]
--operation mode is arithmetic

C1_fre_N[2]_carry_eqn = C1L6;
C1_fre_N[2]_lut_out = C1_fre_N[2] $ (!C1_fre_N[2]_carry_eqn);
C1_fre_N[2] = DFFEAS(C1_fre_N[2]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L8 is div:inst7|fre_N[2]~428
--operation mode is arithmetic

C1L8 = CARRY(C1_fre_N[2] & (!C1L6));


--C1_fre_N[3] is div:inst7|fre_N[3]
--operation mode is arithmetic

C1_fre_N[3]_carry_eqn = C1L8;
C1_fre_N[3]_lut_out = C1_fre_N[3] $ (C1_fre_N[3]_carry_eqn);
C1_fre_N[3] = DFFEAS(C1_fre_N[3]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L10 is div:inst7|fre_N[3]~432
--operation mode is arithmetic

C1L10 = CARRY(!C1L8 # !C1_fre_N[3]);


--C1L54 is div:inst7|LessThan~592
--operation mode is normal

C1L54 = !C1_fre_N[3] # !C1_fre_N[2] # !C1_fre_N[1] # !C1_fre_N[0];


--C1_fre_N[4] is div:inst7|fre_N[4]
--operation mode is arithmetic

C1_fre_N[4]_carry_eqn = C1L10;
C1_fre_N[4]_lut_out = C1_fre_N[4] $ (!C1_fre_N[4]_carry_eqn);
C1_fre_N[4] = DFFEAS(C1_fre_N[4]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L12 is div:inst7|fre_N[4]~436
--operation mode is arithmetic

C1L12 = CARRY(C1_fre_N[4] & (!C1L10));


--C1_fre_N[5] is div:inst7|fre_N[5]
--operation mode is arithmetic

C1_fre_N[5]_carry_eqn = C1L12;
C1_fre_N[5]_lut_out = C1_fre_N[5] $ (C1_fre_N[5]_carry_eqn);
C1_fre_N[5] = DFFEAS(C1_fre_N[5]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L14 is div:inst7|fre_N[5]~440
--operation mode is arithmetic

C1L14 = CARRY(!C1L12 # !C1_fre_N[5]);


--C1L55 is div:inst7|LessThan~593
--operation mode is normal

C1L55 = C1L54 # !C1_fre_N[5] # !C1_fre_N[4];


--C1_fre_N[7] is div:inst7|fre_N[7]
--operation mode is arithmetic

C1_fre_N[7]_carry_eqn = C1L16;
C1_fre_N[7]_lut_out = C1_fre_N[7] $ (C1_fre_N[7]_carry_eqn);
C1_fre_N[7] = DFFEAS(C1_fre_N[7]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L18 is div:inst7|fre_N[7]~444
--operation mode is arithmetic

C1L18 = CARRY(!C1L16 # !C1_fre_N[7]);


--C1_fre_N[8] is div:inst7|fre_N[8]
--operation mode is arithmetic

C1_fre_N[8]_carry_eqn = C1L18;
C1_fre_N[8]_lut_out = C1_fre_N[8] $ (!C1_fre_N[8]_carry_eqn);
C1_fre_N[8] = DFFEAS(C1_fre_N[8]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L20 is div:inst7|fre_N[8]~448
--operation mode is arithmetic

C1L20 = CARRY(C1_fre_N[8] & (!C1L18));


--C1_fre_N[9] is div:inst7|fre_N[9]
--operation mode is arithmetic

C1_fre_N[9]_carry_eqn = C1L20;
C1_fre_N[9]_lut_out = C1_fre_N[9] $ (C1_fre_N[9]_carry_eqn);
C1_fre_N[9] = DFFEAS(C1_fre_N[9]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L22 is div:inst7|fre_N[9]~452
--operation mode is arithmetic

C1L22 = CARRY(!C1L20 # !C1_fre_N[9]);


--C1_fre_N[10] is div:inst7|fre_N[10]
--operation mode is arithmetic

C1_fre_N[10]_carry_eqn = C1L22;
C1_fre_N[10]_lut_out = C1_fre_N[10] $ (!C1_fre_N[10]_carry_eqn);
C1_fre_N[10] = DFFEAS(C1_fre_N[10]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L24 is div:inst7|fre_N[10]~456
--operation mode is arithmetic

C1L24 = CARRY(C1_fre_N[10] & (!C1L22));


--C1L56 is div:inst7|LessThan~594
--operation mode is normal

C1L56 = !C1_fre_N[7] & !C1_fre_N[8] & !C1_fre_N[9] & !C1_fre_N[10];


--C1_fre_N[6] is div:inst7|fre_N[6]
--operation mode is arithmetic

C1_fre_N[6]_carry_eqn = C1L14;
C1_fre_N[6]_lut_out = C1_fre_N[6] $ (!C1_fre_N[6]_carry_eqn);
C1_fre_N[6] = DFFEAS(C1_fre_N[6]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L16 is div:inst7|fre_N[6]~460
--operation mode is arithmetic

C1L16 = CARRY(C1_fre_N[6] & (!C1L14));


--C1_fre_N[11] is div:inst7|fre_N[11]
--operation mode is arithmetic

C1_fre_N[11]_carry_eqn = C1L24;
C1_fre_N[11]_lut_out = C1_fre_N[11] $ (C1_fre_N[11]_carry_eqn);
C1_fre_N[11] = DFFEAS(C1_fre_N[11]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L26 is div:inst7|fre_N[11]~464
--operation mode is arithmetic

C1L26 = CARRY(!C1L24 # !C1_fre_N[11]);


--C1_fre_N[12] is div:inst7|fre_N[12]
--operation mode is arithmetic

C1_fre_N[12]_carry_eqn = C1L26;
C1_fre_N[12]_lut_out = C1_fre_N[12] $ (!C1_fre_N[12]_carry_eqn);
C1_fre_N[12] = DFFEAS(C1_fre_N[12]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L28 is div:inst7|fre_N[12]~468
--operation mode is arithmetic

C1L28 = CARRY(C1_fre_N[12] & (!C1L26));


--C1_fre_N[13] is div:inst7|fre_N[13]
--operation mode is arithmetic

C1_fre_N[13]_carry_eqn = C1L28;
C1_fre_N[13]_lut_out = C1_fre_N[13] $ (C1_fre_N[13]_carry_eqn);
C1_fre_N[13] = DFFEAS(C1_fre_N[13]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L30 is div:inst7|fre_N[13]~472
--operation mode is arithmetic

C1L30 = CARRY(!C1L28 # !C1_fre_N[13]);


--C1_fre_N[14] is div:inst7|fre_N[14]
--operation mode is arithmetic

C1_fre_N[14]_carry_eqn = C1L30;
C1_fre_N[14]_lut_out = C1_fre_N[14] $ (!C1_fre_N[14]_carry_eqn);
C1_fre_N[14] = DFFEAS(C1_fre_N[14]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L32 is div:inst7|fre_N[14]~476
--operation mode is arithmetic

C1L32 = CARRY(C1_fre_N[14] & (!C1L30));


--C1L57 is div:inst7|LessThan~595
--operation mode is normal

C1L57 = !C1_fre_N[14] # !C1_fre_N[13] # !C1_fre_N[12] # !C1_fre_N[11];


--C1L58 is div:inst7|LessThan~596
--operation mode is normal

C1L58 = C1L57 # C1L55 & C1L56 & !C1_fre_N[6];


--C1L59 is div:inst7|LessThan~597
--operation mode is normal

C1L59 = C1L53 # !C1_fre_N[17] & !C1_fre_N[15] & C1L58;


--C1L60 is div:inst7|LessThan~598
--operation mode is normal

C1L60 = C1_fre_N[24] & (C1_fre_N[23] # !C1L52 & !C1L59);


--B1_key_7279_tmp[7] is FPGA_7279:inst|key_7279_tmp[7]
--operation mode is normal

B1_key_7279_tmp[7]_lut_out = B1L19 & A1L8 # !B1L19 & (B1_key_7279_tmp[7]);
B1_key_7279_tmp[7] = DFFEAS(B1_key_7279_tmp[7]_lut_out, !C2_clk_tmp, VCC, , , , , , );


--B1_state.shift_key_high1 is FPGA_7279:inst|state.shift_key_high1
--operation mode is normal

B1_state.shift_key_high1_lut_out = B1_state.shift_key_high;
B1_state.shift_key_high1 = DFFEAS(B1_state.shift_key_high1_lut_out, !C2_clk_tmp, SYS_RST_N, , , , , , );


--B1_sdata_cnt[2] is FPGA_7279:inst|sdata_cnt[2]
--operation mode is normal

B1_sdata_cnt[2]_lut_out = B1L67 & (B1_state.next_delay # B1_sdata_cnt[2] $ !B1L52) # !B1L67 & B1_sdata_cnt[2];
B1_sdata_cnt[2] = DFFEAS(B1_sdata_cnt[2]_lut_out, !C2_clk_tmp, VCC, , , , , , );


--B1_sdata_cnt[1] is FPGA_7279:inst|sdata_cnt[1]
--operation mode is normal

B1_sdata_cnt[1]_lut_out = B1_state.next_delay # B1_sdata_cnt[1] $ !B1_sdata_cnt[0];
B1_sdata_cnt[1] = DFFEAS(B1_sdata_cnt[1]_lut_out, !C2_clk_tmp, VCC, , B1L67, , , , );


--B1_sdata_cnt[0] is FPGA_7279:inst|sdata_cnt[0]
--operation mode is normal

B1_sdata_cnt[0]_lut_out = B1_state.next_delay # !B1_sdata_cnt[0];
B1_sdata_cnt[0] = DFFEAS(B1_sdata_cnt[0]_lut_out, !C2_clk_tmp, VCC, , B1L67, , , , );


--B1L52 is FPGA_7279:inst|LessThan~111
--operation mode is normal

B1L52 = B1_sdata_cnt[1] # B1_sdata_cnt[0];


--B1L42 is FPGA_7279:inst|key_7279[7]~54
--operation mode is normal

B1L42 = B1_state.shift_key_high1 & !B1_sdata_cnt[2] & !B1L52 & !KEY7279;


--B1_key_7279_tmp[6] is FPGA_7279:inst|key_7279_tmp[6]
--operation mode is normal

B1_key_7279_tmp[6]_lut_out = B1L20 & A1L8 # !B1L20 & (B1_key_7279_tmp[6]);
B1_key_7279_tmp[6] = DFFEAS(B1_key_7279_tmp[6]_lut_out, !C2_clk_tmp, VCC, , , , , , );


--B1_key_7279_tmp[5] is FPGA_7279:inst|key_7279_tmp[5]
--operation mode is normal

B1_key_7279_tmp[5]_lut_out = B1L21 & A1L8 # !B1L21 & (B1_key_7279_tmp[5]);
B1_key_7279_tmp[5] = DFFEAS(B1_key_7279_tmp[5]_lut_out, !C2_clk_tmp, VCC, , , , , , );


--B1_key_7279_tmp[4] is FPGA_7279:inst|key_7279_tmp[4]
--operation mode is normal

B1_key_7279_tmp[4]_lut_out = B1L22 & A1L8 # !B1L22 & (B1_key_7279_tmp[4]);
B1_key_7279_tmp[4] = DFFEAS(B1_key_7279_tmp[4]_lut_out, !C2_clk_tmp, VCC, , , , , , );


--B1_key_7279_tmp[3] is FPGA_7279:inst|key_7279_tmp[3]
--operation mode is normal

B1_key_7279_tmp[3]_lut_out = B1L23 & A1L8 # !B1L23 & (B1_key_7279_tmp[3]);
B1_key_7279_tmp[3] = DFFEAS(B1_key_7279_tmp[3]_lut_out, !C2_clk_tmp, VCC, , , , , , );


--B1_key_7279_tmp[2] is FPGA_7279:inst|key_7279_tmp[2]
--operation mode is normal

B1_key_7279_tmp[2]_lut_out = B1L24 & A1L8 # !B1L24 & (B1_key_7279_tmp[2]);
B1_key_7279_tmp[2] = DFFEAS(B1_key_7279_tmp[2]_lut_out, !C2_clk_tmp, VCC, , , , , , );


--B1_key_7279_tmp[1] is FPGA_7279:inst|key_7279_tmp[1]
--operation mode is normal

B1_key_7279_tmp[1]_lut_out = B1L25 & A1L8 # !B1L25 & (B1_key_7279_tmp[1]);
B1_key_7279_tmp[1] = DFFEAS(B1_key_7279_tmp[1]_lut_out, !C2_clk_tmp, VCC, , , , , , );


--B1_key_7279_tmp[0] is FPGA_7279:inst|key_7279_tmp[0]
--operation mode is normal

B1_key_7279_tmp[0]_lut_out = B1L26 & A1L8 # !B1L26 & (B1_key_7279_tmp[0]);
B1_key_7279_tmp[0] = DFFEAS(B1_key_7279_tmp[0]_lut_out, !C2_clk_tmp, VCC, , , , , , );


--B1_state.shift_data_high is FPGA_7279:inst|state.shift_data_high
--operation mode is normal

B1_state.shift_data_high_lut_out = B1_state.shift_data_low;
B1_state.shift_data_high = DFFEAS(B1_state.shift_data_high_lut_out, !C2_clk_tmp, SYS_RST_N, , , , , , );


--B1L75 is FPGA_7279:inst|Select~1061
--operation mode is normal

B1L75 = !B1_sdata_cnt[2] & !B1L52 & (B1_state.shift_key_high1 # B1_state.shift_data_high);


--B1_state.shift_cmd_high is FPGA_7279:inst|state.shift_cmd_high
--operation mode is normal

B1_state.shift_cmd_high_lut_out = B1_state.shift_cmd_low;
B1_state.shift_cmd_high = DFFEAS(B1_state.shift_cmd_high_lut_out, !C2_clk_tmp, SYS_RST_N, , , , , , );


--B1_scmd_cnt[2] is FPGA_7279:inst|scmd_cnt[2]
--operation mode is normal

B1_scmd_cnt[2]_lut_out = B1L62 & (B1_scmd_cnt[2] $ !B1L53 # !B1_state.shift_cmd_high) # !B1L62 & B1_scmd_cnt[2];
B1_scmd_cnt[2] = DFFEAS(B1_scmd_cnt[2]_lut_out, !C2_clk_tmp, VCC, , , , , , );


--B1_scmd_cnt[1] is FPGA_7279:inst|scmd_cnt[1]
--operation mode is normal

B1_scmd_cnt[1]_lut_out = B1_scmd_cnt[1] $ !B1_scmd_cnt[0] # !B1_state.shift_cmd_high;
B1_scmd_cnt[1] = DFFEAS(B1_scmd_cnt[1]_lut_out, !C2_clk_tmp, VCC, , B1L62, , , , );


--B1_scmd_cnt[0] is FPGA_7279:inst|scmd_cnt[0]
--operation mode is normal

B1_scmd_cnt[0]_lut_out = !B1_scmd_cnt[0] # !B1_state.shift_cmd_high;
B1_scmd_cnt[0] = DFFEAS(B1_scmd_cnt[0]_lut_out, !C2_clk_tmp, VCC, , B1L62, , , , );


--B1L76 is FPGA_7279:inst|Select~1062
--operation mode is normal

B1L76 = B1_state.shift_cmd_high & !B1_scmd_cnt[2] & !B1_scmd_cnt[1] & !B1_scmd_cnt[0];


--B1_data_start_tmp is FPGA_7279:inst|data_start_tmp
--operation mode is normal