e-try.map.eqn

频率计编程 看看吧第一次先贴希望对大家有用

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--B1_CS7279 is FPGA_7279:inst|CS7279
--operation mode is normal

B1_CS7279_lut_out = !B1_state.finish & (B1_CS7279 # B1_state.start);
B1_CS7279 = DFFEAS(B1_CS7279_lut_out, !C2_clk_tmp, SYS_RST_N, , , , , , );


--B1_CLK7279 is FPGA_7279:inst|CLK7279
--operation mode is normal

B1_CLK7279_lut_out = B1_CLK7279 & (B1_state.shift_key_high # !B1L74) # !B1L73;
B1_CLK7279 = DFFEAS(B1_CLK7279_lut_out, !C2_clk_tmp, SYS_RST_N, , , , , , );


--C3_clk_tmp is div:inst6|clk_tmp
--operation mode is normal

C3_clk_tmp_lut_out = C3_clk_tmp $ (C3L15 & (SYS_RST_N));
C3_clk_tmp = DFFEAS(C3_clk_tmp_lut_out, !SYS_CLK, VCC, , , , , , );


--C2_clk_tmp is div:inst1|clk_tmp
--operation mode is normal

C2_clk_tmp_lut_out = C2_clk_tmp $ (C2L20 & (SYS_RST_N));
C2_clk_tmp = DFFEAS(C2_clk_tmp_lut_out, !SYS_CLK, VCC, , , , , , );


--C1_clk_tmp is div:inst7|clk_tmp
--operation mode is normal

C1_clk_tmp_lut_out = C1_clk_tmp $ (C1L60 & (SYS_RST_N));
C1_clk_tmp = DFFEAS(C1_clk_tmp_lut_out, !SYS_CLK, VCC, , , , , , );


--B1_key_7279[7] is FPGA_7279:inst|key_7279[7]
--operation mode is normal

B1_key_7279[7]_lut_out = B1_key_7279_tmp[7];
B1_key_7279[7] = DFFEAS(B1_key_7279[7]_lut_out, !C2_clk_tmp, SYS_RST_N, , B1L42, , , , );


--B1_key_7279[6] is FPGA_7279:inst|key_7279[6]
--operation mode is normal

B1_key_7279[6]_lut_out = B1_key_7279_tmp[6];
B1_key_7279[6] = DFFEAS(B1_key_7279[6]_lut_out, !C2_clk_tmp, SYS_RST_N, , B1L42, , , , );


--B1_key_7279[5] is FPGA_7279:inst|key_7279[5]
--operation mode is normal

B1_key_7279[5]_lut_out = B1_key_7279_tmp[5];
B1_key_7279[5] = DFFEAS(B1_key_7279[5]_lut_out, !C2_clk_tmp, SYS_RST_N, , B1L42, , , , );


--B1_key_7279[4] is FPGA_7279:inst|key_7279[4]
--operation mode is normal

B1_key_7279[4]_lut_out = B1_key_7279_tmp[4];
B1_key_7279[4] = DFFEAS(B1_key_7279[4]_lut_out, !C2_clk_tmp, SYS_RST_N, , B1L42, , , , );


--B1_key_7279[3] is FPGA_7279:inst|key_7279[3]
--operation mode is normal

B1_key_7279[3]_lut_out = B1_key_7279_tmp[3];
B1_key_7279[3] = DFFEAS(B1_key_7279[3]_lut_out, !C2_clk_tmp, SYS_RST_N, , B1L42, , , , );


--B1_key_7279[2] is FPGA_7279:inst|key_7279[2]
--operation mode is normal

B1_key_7279[2]_lut_out = B1_key_7279_tmp[2];
B1_key_7279[2] = DFFEAS(B1_key_7279[2]_lut_out, !C2_clk_tmp, SYS_RST_N, , B1L42, , , , );


--B1_key_7279[1] is FPGA_7279:inst|key_7279[1]
--operation mode is normal

B1_key_7279[1]_lut_out = B1_key_7279_tmp[1];
B1_key_7279[1] = DFFEAS(B1_key_7279[1]_lut_out, !C2_clk_tmp, SYS_RST_N, , B1L42, , , , );


--B1_key_7279[0] is FPGA_7279:inst|key_7279[0]
--operation mode is normal

B1_key_7279[0]_lut_out = B1_key_7279_tmp[0];
B1_key_7279[0] = DFFEAS(B1_key_7279[0]_lut_out, !C2_clk_tmp, SYS_RST_N, , B1L42, , , , );


--B1_state.finish is FPGA_7279:inst|state.finish
--operation mode is normal

B1_state.finish_lut_out = B1L75 # B1L76 & (!B1L54);
B1_state.finish = DFFEAS(B1_state.finish_lut_out, !C2_clk_tmp, SYS_RST_N, , , , , , );


--B1_state.start is FPGA_7279:inst|state.start
--operation mode is normal

B1_state.start_lut_out = !B1_state.idle;
B1_state.start = DFFEAS(B1_state.start_lut_out, !C2_clk_tmp, SYS_RST_N, , , , , , );


--B1_state.shift_key_high is FPGA_7279:inst|state.shift_key_high
--operation mode is normal

B1_state.shift_key_high_lut_out = B1_state.shift_key_low;
B1_state.shift_key_high = DFFEAS(B1_state.shift_key_high_lut_out, !C2_clk_tmp, SYS_RST_N, , , , , , );


--B1_state.shift_cmd_low is FPGA_7279:inst|state.shift_cmd_low
--operation mode is normal

B1_state.shift_cmd_low_lut_out = B1L78;
B1_state.shift_cmd_low = DFFEAS(B1_state.shift_cmd_low_lut_out, !C2_clk_tmp, SYS_RST_N, , , , , , );


--B1_state.shift_data_low is FPGA_7279:inst|state.shift_data_low
--operation mode is normal

B1_state.shift_data_low_lut_out = B1L79 # B1_state.next_delay & !B1_delay_cnt[1] & !A1L22;
B1_state.shift_data_low = DFFEAS(B1_state.shift_data_low_lut_out, !C2_clk_tmp, SYS_RST_N, , , , , , );


--B1_state.shift_key_low is FPGA_7279:inst|state.shift_key_low
--operation mode is normal

B1_state.shift_key_low_lut_out = B1L81 # B1_state.next_delay & !B1_delay_cnt[1] & A1L22;
B1_state.shift_key_low = DFFEAS(B1_state.shift_key_low_lut_out, !C2_clk_tmp, SYS_RST_N, , , , , , );


--B1L73 is FPGA_7279:inst|Select~1058
--operation mode is normal

B1L73 = !B1_state.shift_cmd_low & !B1_state.shift_data_low & !B1_state.shift_key_low;


--B1_state.next_delay is FPGA_7279:inst|state.next_delay
--operation mode is normal

B1_state.next_delay_lut_out = B1_state.next_delay & (B1_delay_cnt[1] # B1L54 & B1L76) # !B1_state.next_delay & B1L54 & B1L76;
B1_state.next_delay = DFFEAS(B1_state.next_delay_lut_out, !C2_clk_tmp, SYS_RST_N, , , , , , );


--B1_state.start_delay is FPGA_7279:inst|state.start_delay
--operation mode is normal

B1_state.start_delay_lut_out = B1_state.start # B1_state.start_delay & B1_delay_cnt[1];
B1_state.start_delay = DFFEAS(B1_state.start_delay_lut_out, !C2_clk_tmp, SYS_RST_N, , , , , , );


--B1_state.idle is FPGA_7279:inst|state.idle
--operation mode is normal

B1_state.idle_lut_out = !B1_state.finish;
B1_state.idle = DFFEAS(B1_state.idle_lut_out, !C2_clk_tmp, SYS_RST_N, , , , , , );


--B1L74 is FPGA_7279:inst|Select~1059
--operation mode is normal

B1L74 = !B1_state.next_delay & !B1_state.start_delay & !B1_state.finish & B1_state.idle;


--C3_fre_N[0] is div:inst6|fre_N[0]
--operation mode is arithmetic

C3_fre_N[0]_lut_out = !C3_fre_N[0];
C3_fre_N[0] = DFFEAS(C3_fre_N[0]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C3L15, );

--C3L4 is div:inst6|fre_N[0]~124
--operation mode is arithmetic

C3L4 = CARRY(C3_fre_N[0]);


--C3_fre_N[1] is div:inst6|fre_N[1]
--operation mode is arithmetic

C3_fre_N[1]_carry_eqn = C3L4;
C3_fre_N[1]_lut_out = C3_fre_N[1] $ (C3_fre_N[1]_carry_eqn);
C3_fre_N[1] = DFFEAS(C3_fre_N[1]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C3L15, );

--C3L6 is div:inst6|fre_N[1]~128
--operation mode is arithmetic

C3L6 = CARRY(!C3L4 # !C3_fre_N[1]);


--C3_fre_N[2] is div:inst6|fre_N[2]
--operation mode is arithmetic

C3_fre_N[2]_carry_eqn = C3L6;
C3_fre_N[2]_lut_out = C3_fre_N[2] $ (!C3_fre_N[2]_carry_eqn);
C3_fre_N[2] = DFFEAS(C3_fre_N[2]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C3L15, );

--C3L8 is div:inst6|fre_N[2]~132
--operation mode is arithmetic

C3L8 = CARRY(C3_fre_N[2] & (!C3L6));


--C3_fre_N[3] is div:inst6|fre_N[3]
--operation mode is arithmetic

C3_fre_N[3]_carry_eqn = C3L8;
C3_fre_N[3]_lut_out = C3_fre_N[3] $ (C3_fre_N[3]_carry_eqn);
C3_fre_N[3] = DFFEAS(C3_fre_N[3]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C3L15, );

--C3L10 is div:inst6|fre_N[3]~136
--operation mode is arithmetic

C3L10 = CARRY(!C3L8 # !C3_fre_N[3]);


--C3L11 is div:inst6|fre_N[3]~139
--operation mode is normal

C3L11 = !C3_fre_N[0] & !C3_fre_N[1] & !C3_fre_N[2] & !C3_fre_N[3];


--C3_fre_N[4] is div:inst6|fre_N[4]
--operation mode is arithmetic

C3_fre_N[4]_carry_eqn = C3L10;
C3_fre_N[4]_lut_out = C3_fre_N[4] $ (!C3_fre_N[4]_carry_eqn);
C3_fre_N[4] = DFFEAS(C3_fre_N[4]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C3L15, );

--C3L13 is div:inst6|fre_N[4]~141
--operation mode is arithmetic

C3L13 = CARRY(C3_fre_N[4] & (!C3L10));


--C3_fre_N[5] is div:inst6|fre_N[5]
--operation mode is normal

C3_fre_N[5]_carry_eqn = C3L13;
C3_fre_N[5]_lut_out = C3_fre_N[5] $ (C3_fre_N[5]_carry_eqn);
C3_fre_N[5] = DFFEAS(C3_fre_N[5]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C3L15, );


--C3L15 is div:inst6|LessThan~65
--operation mode is normal

C3L15 = !C3L11 & (C3_fre_N[4] & C3_fre_N[5]);


--C2_fre_N[0] is div:inst1|fre_N[0]
--operation mode is arithmetic

C2_fre_N[0]_lut_out = !C2_fre_N[0];
C2_fre_N[0] = DFFEAS(C2_fre_N[0]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C2L20, );

--C2L4 is div:inst1|fre_N[0]~120
--operation mode is arithmetic

C2L4 = CARRY(C2_fre_N[0]);


--C2_fre_N[1] is div:inst1|fre_N[1]
--operation mode is arithmetic

C2_fre_N[1]_carry_eqn = C2L4;
C2_fre_N[1]_lut_out = C2_fre_N[1] $ (C2_fre_N[1]_carry_eqn);
C2_fre_N[1] = DFFEAS(C2_fre_N[1]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C2L20, );

--C2L6 is div:inst1|fre_N[1]~124
--operation mode is arithmetic

C2L6 = CARRY(!C2L4 # !C2_fre_N[1]);


--C2_fre_N[2] is div:inst1|fre_N[2]
--operation mode is arithmetic

C2_fre_N[2]_carry_eqn = C2L6;
C2_fre_N[2]_lut_out = C2_fre_N[2] $ (!C2_fre_N[2]_carry_eqn);
C2_fre_N[2] = DFFEAS(C2_fre_N[2]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C2L20, );

--C2L8 is div:inst1|fre_N[2]~128
--operation mode is arithmetic

C2L8 = CARRY(C2_fre_N[2] & (!C2L6));


--C2_fre_N[3] is div:inst1|fre_N[3]
--operation mode is arithmetic

C2_fre_N[3]_carry_eqn = C2L8;
C2_fre_N[3]_lut_out = C2_fre_N[3] $ (C2_fre_N[3]_carry_eqn);
C2_fre_N[3] = DFFEAS(C2_fre_N[3]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C2L20, );

--C2L10 is div:inst1|fre_N[3]~132
--operation mode is arithmetic

C2L10 = CARRY(!C2L8 # !C2_fre_N[3]);


--C2L18 is div:inst1|LessThan~118
--operation mode is normal

C2L18 = !C2_fre_N[3] & (!C2_fre_N[2] # !C2_fre_N[1] # !C2_fre_N[0]);


--C2_fre_N[4] is div:inst1|fre_N[4]
--operation mode is arithmetic

C2_fre_N[4]_carry_eqn = C2L10;
C2_fre_N[4]_lut_out = C2_fre_N[4] $ (!C2_fre_N[4]_carry_eqn);
C2_fre_N[4] = DFFEAS(C2_fre_N[4]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C2L20, );

--C2L12 is div:inst1|fre_N[4]~136
--operation mode is arithmetic

C2L12 = CARRY(C2_fre_N[4] & (!C2L10));


--C2_fre_N[5] is div:inst1|fre_N[5]
--operation mode is arithmetic

C2_fre_N[5]_carry_eqn = C2L12;
C2_fre_N[5]_lut_out = C2_fre_N[5] $ (C2_fre_N[5]_carry_eqn);
C2_fre_N[5] = DFFEAS(C2_fre_N[5]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C2L20, );

--C2L14 is div:inst1|fre_N[5]~140
--operation mode is arithmetic

C2L14 = CARRY(!C2L12 # !C2_fre_N[5]);


--C2L19 is div:inst1|LessThan~119
--operation mode is normal

C2L19 = !C2_fre_N[4] & !C2_fre_N[5];


--C2_fre_N[6] is div:inst1|fre_N[6]
--operation mode is arithmetic

C2_fre_N[6]_carry_eqn = C2L14;
C2_fre_N[6]_lut_out = C2_fre_N[6] $ (!C2_fre_N[6]_carry_eqn);
C2_fre_N[6] = DFFEAS(C2_fre_N[6]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C2L20, );

--C2L16 is div:inst1|fre_N[6]~144
--operation mode is arithmetic

C2L16 = CARRY(C2_fre_N[6] & (!C2L14));


--C2_fre_N[7] is div:inst1|fre_N[7]
--operation mode is normal

C2_fre_N[7]_carry_eqn = C2L16;
C2_fre_N[7]_lut_out = C2_fre_N[7] $ (C2_fre_N[7]_carry_eqn);
C2_fre_N[7] = DFFEAS(C2_fre_N[7]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C2L20, );


--C2L20 is div:inst1|LessThan~120
--operation mode is normal

C2L20 = C2_fre_N[6] & C2_fre_N[7] & (!C2L19 # !C2L18);


--C1_fre_N[23] is div:inst7|fre_N[23]
--operation mode is arithmetic

C1_fre_N[23]_carry_eqn = C1L48;
C1_fre_N[23]_lut_out = C1_fre_N[23] $ (C1_fre_N[23]_carry_eqn);
C1_fre_N[23] = DFFEAS(C1_fre_N[23]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L50 is div:inst7|fre_N[23]~380
--operation mode is arithmetic

C1L50 = CARRY(!C1L48 # !C1_fre_N[23]);


--C1_fre_N[17] is div:inst7|fre_N[17]
--operation mode is arithmetic

C1_fre_N[17]_carry_eqn = C1L36;
C1_fre_N[17]_lut_out = C1_fre_N[17] $ (C1_fre_N[17]_carry_eqn);
C1_fre_N[17] = DFFEAS(C1_fre_N[17]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L38 is div:inst7|fre_N[17]~384
--operation mode is arithmetic

C1L38 = CARRY(!C1L36 # !C1_fre_N[17]);


--C1_fre_N[16] is div:inst7|fre_N[16]
--operation mode is arithmetic

C1_fre_N[16]_carry_eqn = C1L34;
C1_fre_N[16]_lut_out = C1_fre_N[16] $ (!C1_fre_N[16]_carry_eqn);
C1_fre_N[16] = DFFEAS(C1_fre_N[16]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L36 is div:inst7|fre_N[16]~388
--operation mode is arithmetic

C1L36 = CARRY(C1_fre_N[16] & (!C1L34));


--C1_fre_N[18] is div:inst7|fre_N[18]
--operation mode is arithmetic

C1_fre_N[18]_carry_eqn = C1L38;
C1_fre_N[18]_lut_out = C1_fre_N[18] $ (!C1_fre_N[18]_carry_eqn);
C1_fre_N[18] = DFFEAS(C1_fre_N[18]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L40 is div:inst7|fre_N[18]~392
--operation mode is arithmetic

C1L40 = CARRY(C1_fre_N[18] & (!C1L38));


--C1_fre_N[19] is div:inst7|fre_N[19]
--operation mode is arithmetic

C1_fre_N[19]_carry_eqn = C1L40;
C1_fre_N[19]_lut_out = C1_fre_N[19] $ (C1_fre_N[19]_carry_eqn);
C1_fre_N[19] = DFFEAS(C1_fre_N[19]_lut_out, !SYS_CLK, SYS_RST_N, , , , , C1L60, );

--C1L42 is div:inst7|fre_N[19]~396
--operation mode is arithmetic

C1L42 = CARRY(!C1L40 # !C1_fre_N[19]);


--C1L52 is div:inst7|LessThan~590
--operation mode is normal

C1L52 = !C1_fre_N[17] & !C1_fre_N[16] # !C1_fre_N[19] # !C1_fre_N[18];