📄 descript.a
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;************************************************************************
; MODULE : descript.a *
; PURPOSE: Descritor Table Code(920T) *
; VERSION: Version 0.1(cache,mmu on) *
; written by CES *
; Copyright(2000-3) samsung electoronics corp. *
; 2/23/2000 *
; 3/30/2000 *
; 4/07/2000 *
; 5/17/2000 *
;************************************************************************
;MMU descriptor table
L1_DESC_BASE_ADDR EQU 0x8F90000 ;configuration when memory size is 16MB
;************************************************************************
;MMU level1 descriptor table address(section:1MB)
;************************************************************************
;Memory configuration
;0x0000000 ~ 0x1FFFFFF : ROM0(32MB)
;0x2000000 ~ 0x3FFFFFF : ROM1(32MB)
;0x4000000 ~ 0x5FFFFFF : ESRAM(32MB)
;0x6000000 ~ 0x6FFFFFF : ISRAM0(16MB)
;0x7000000 ~ 0x7FFFFFF : ISRAM1(16MB)
;0x8000000 ~ 0x9FFFFFF : SDRAM0(32MB)
;0xA000000 ~ 0xBFFFFFF : SDRAM1(32MB)
;0xC000000 ~ 0xCFFFFFF : IO region(16MB)
;***********************************************************************
;Number of entries: 4096, size: 16KB boundary
L1DTA_ROM0 EQU L1_DESC_BASE_ADDR
L1DTA_ROM1 EQU (L1DTA_ROM0 + (32*4))
L1DTA_ESRAM EQU (L1DTA_ROM1 + (32*4))
L1DTA_ISRAM0 EQU (L1DTA_ESRAM + (32*4))
L1DTA_ISRAM1 EQU (L1DTA_ISRAM0 + (16*4))
L1DTA_SDRAM01 EQU (L1DTA_ISRAM1 + (16*4))
L1DTA_SDRAM02 EQU (L1DTA_SDRAM01 + (8*4))
L1DTA_SDRAM03 EQU (L1DTA_SDRAM02 + (8*4))
L1DTA_SDRAM04 EQU (L1DTA_SDRAM03 + (8*4))
L1DTA_SDRAM1 EQU (L1DTA_SDRAM04 + (8*4))
L1DTA_IOR EQU (L1DTA_SDRAM1 + (32*4))
L1DTA_UND0 EQU (L1DTA_IOR + (16*4))
L1DTA_UND1 EQU (L1DTA_UND0 + (48*4))
L2_DESC_BASE_ADDR EQU 0x8F80000
;************************************************************************
;IOR level2 descriptor table address(small page:4KB)
;************************************************************************
;Number of entries: 256, size: 1KB boundary
;IO space configuration
;0xC000000 ~ 0xC00FFFF : ARM920T slave(64KB)
;0xC010000 ~ 0xC01FFFF : Meomry controller(64KB)
;0xC020000 ~ 0xC02FFFF : DMA controller(64KB)
;0xC030000 ~ 0xC03FFFF : LCD controller(64KB)
;0xC040000 ~ 0xC04FFFF : Ethernet MAC(64KB)
;0xC050000 ~ 0xC05FFFF : X memory(64KB)
;0xC060000 ~ 0xC06FFFF : Y memory(64KB)
;0xC070000 ~ 0xC07FFFF : P memory(64KB)
;0xC080000 ~ 0xC0AFFFF : AHB2APB bridge(192KB)
;0xC0B0000 ~ 0xC0BFFFF : Tube(debug)
;************************************************************************
L2DTA_IOR0 EQU L2_DESC_BASE_ADDR ;APB bridge
L2DTA_IOR1 EQU (L2DTA_IOR0 + (16*4)) ;Memory controller
L2DTA_IOR2 EQU (L2DTA_IOR1 + (16*4)) ;DMA controller
L2DTA_IOR3 EQU (L2DTA_IOR2 + (16*4)) ;LCD controller
L2DTA_IOR4 EQU (L2DTA_IOR3 + (16*4)) ;Ethernet MAC
L2DTA_IOR5 EQU (L2DTA_IOR4 + (16*4)) ;X memory
L2DTA_IOR5_1 EQU (L2DTA_IOR5 + 4) ;X memory
L2DTA_IOR5_2 EQU (L2DTA_IOR5_1 + 4) ;X memory
L2DTA_IOR5_3 EQU (L2DTA_IOR5_2 + 4) ;X memory
L2DTA_IOR5_4 EQU (L2DTA_IOR5_3 + 4) ;X memory
L2DTA_IOR5_5 EQU (L2DTA_IOR5_4 + 4) ;X memory
L2DTA_IOR5_6 EQU (L2DTA_IOR5_5 + 4) ;X memory
L2DTA_IOR5_7 EQU (L2DTA_IOR5_6 + 4) ;X memory
L2DTA_IOR5_8 EQU (L2DTA_IOR5_7 + 4) ;X memory
L2DTA_IOR5_9 EQU (L2DTA_IOR5_8 + 4) ;X memory
L2DTA_IOR5_10 EQU (L2DTA_IOR5_9 + 4) ;X memory
L2DTA_IOR5_11 EQU (L2DTA_IOR5_10 + 4) ;X memory
L2DTA_IOR5_12 EQU (L2DTA_IOR5_11 + 4) ;X memory
L2DTA_IOR5_13 EQU (L2DTA_IOR5_12 + 4) ;X memory
L2DTA_IOR5_14 EQU (L2DTA_IOR5_13 + 4) ;X memory
L2DTA_IOR5_15 EQU (L2DTA_IOR5_14 + 4) ;X memory
L2DTA_IOR6 EQU (L2DTA_IOR5_15 + 4) ;Y memory
L2DTA_IOR6_1 EQU (L2DTA_IOR6 + 4) ;Y memory
L2DTA_IOR6_2 EQU (L2DTA_IOR6_1 + 4) ;Y memory
L2DTA_IOR6_3 EQU (L2DTA_IOR6_2 + 4) ;Y memory
L2DTA_IOR6_4 EQU (L2DTA_IOR6_3 + 4) ;Y memory
L2DTA_IOR6_5 EQU (L2DTA_IOR6_4 + 4) ;Y memory
L2DTA_IOR6_6 EQU (L2DTA_IOR6_5 + 4) ;Y memory
L2DTA_IOR6_7 EQU (L2DTA_IOR6_6 + 4) ;Y memory
L2DTA_IOR6_8 EQU (L2DTA_IOR6_7 + 4) ;Y memory
L2DTA_IOR6_9 EQU (L2DTA_IOR6_8 + 4) ;Y memory
L2DTA_IOR6_10 EQU (L2DTA_IOR6_9 + 4) ;Y memory
L2DTA_IOR6_11 EQU (L2DTA_IOR6_10 + 4) ;Y memory
L2DTA_IOR6_12 EQU (L2DTA_IOR6_11 + 4) ;Y memory
L2DTA_IOR6_13 EQU (L2DTA_IOR6_12 + 4) ;Y memory
L2DTA_IOR6_14 EQU (L2DTA_IOR6_13 + 4) ;Y memory
L2DTA_IOR6_15 EQU (L2DTA_IOR6_14 + 4) ;Y memory
L2DTA_IOR7 EQU (L2DTA_IOR6_15 + 4) ;P memory
L2DTA_IOR7_1 EQU (L2DTA_IOR7 + 4) ;P memory
L2DTA_IOR7_2 EQU (L2DTA_IOR7_1 + 4) ;P memory
L2DTA_IOR7_3 EQU (L2DTA_IOR7_2 + 4) ;P memory
L2DTA_IOR7_4 EQU (L2DTA_IOR7_3 + 4) ;P memory
L2DTA_IOR7_5 EQU (L2DTA_IOR7_4 + 4) ;P memory
L2DTA_IOR7_6 EQU (L2DTA_IOR7_5 + 4) ;P memory
L2DTA_IOR7_7 EQU (L2DTA_IOR7_6 + 4) ;P memory
L2DTA_IOR7_8 EQU (L2DTA_IOR7_7 + 4) ;P memory
L2DTA_IOR7_9 EQU (L2DTA_IOR7_8 + 4) ;P memory
L2DTA_IOR7_10 EQU (L2DTA_IOR7_9 + 4) ;P memory
L2DTA_IOR7_11 EQU (L2DTA_IOR7_10 + 4) ;P memory
L2DTA_IOR7_12 EQU (L2DTA_IOR7_11 + 4) ;P memory
L2DTA_IOR7_13 EQU (L2DTA_IOR7_12 + 4) ;P memory
L2DTA_IOR7_14 EQU (L2DTA_IOR7_13 + 4) ;P memory
L2DTA_IOR7_15 EQU (L2DTA_IOR7_14 + 4) ;P memory
L2DTA_IOR8 EQU (L2DTA_IOR7_15 + 4) ;AHB2APB bridge
L2DTA_IOR8_1 EQU (L2DTA_IOR8 + 4)
L2DTA_IOR8_2 EQU (L2DTA_IOR8_1 + 4)
L2DTA_IOR8_3 EQU (L2DTA_IOR8_2 + 4)
L2DTA_IOR8_4 EQU (L2DTA_IOR8_3 + 4)
L2DTA_IOR8_5 EQU (L2DTA_IOR8_4 + 4)
L2DTA_IOR8_6 EQU (L2DTA_IOR8_5 + 4)
L2DTA_IOR8_7 EQU (L2DTA_IOR8_6 + 4)
L2DTA_IOR8_8 EQU (L2DTA_IOR8_7 + 4)
L2DTA_IOR8_9 EQU (L2DTA_IOR8_8 + 4)
L2DTA_IOR8_10 EQU (L2DTA_IOR8_9 + 4)
L2DTA_IOR8_11 EQU (L2DTA_IOR8_10 + 4)
L2DTA_IOR8_12 EQU (L2DTA_IOR8_11 + 4)
L2DTA_IOR8_13 EQU (L2DTA_IOR8_12 + 4)
L2DTA_IOR8_14 EQU (L2DTA_IOR8_13 + 4)
L2DTA_IOR8_15 EQU (L2DTA_IOR8_14 + 4)
L2DTA_IOR9 EQU (L2DTA_IOR8_15 + 4) ;PCMCIA register
L2DTA_IOR10 EQU (L2DTA_IOR9 + (16*4)) ;PCMCIA attribute memory
L2DTA_IOR10_1 EQU (L2DTA_IOR10 + 4)
L2DTA_IOR10_2 EQU (L2DTA_IOR10_1 + 4)
L2DTA_IOR10_3 EQU (L2DTA_IOR10_2 + 4)
L2DTA_IOR10_4 EQU (L2DTA_IOR10_3 + 4)
L2DTA_IOR10_5 EQU (L2DTA_IOR10_4 + 4)
L2DTA_IOR10_6 EQU (L2DTA_IOR10_5 + 4)
L2DTA_IOR10_7 EQU (L2DTA_IOR10_6 + 4)
L2DTA_IOR10_8 EQU (L2DTA_IOR10_7 + 4)
L2DTA_IOR10_9 EQU (L2DTA_IOR10_8 + 4)
L2DTA_IOR10_10 EQU (L2DTA_IOR10_9 + 4)
L2DTA_IOR10_11 EQU (L2DTA_IOR10_10 + 4)
L2DTA_IOR10_12 EQU (L2DTA_IOR10_11 + 4)
L2DTA_IOR10_13 EQU (L2DTA_IOR10_12 + 4)
L2DTA_IOR10_14 EQU (L2DTA_IOR10_13 + 4)
L2DTA_IOR10_15 EQU (L2DTA_IOR10_14 + 4)
L2DTA_IOR11 EQU (L2DTA_IOR10_15 + 4) ;Tube(debug)
END
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