📄 initmn.s
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; Sdram MMU table descriptor(8MB)
LDR r0, =L1DTSdram02
LDMIA r0, {r1-r8}
LDR r0, =L1DTA_SDRAM02
STMIA r0, {r1-r8}
; I/O region MMU table descriptor(1MB)
LDR r0, =L1DTIor
LDR r1, [r0]
LDR r2, =L1DTA_IOR
STR r1, [r2]
; Level2
; I/O region(ARM920T) - 4/64KB
LDR r0, =L2DTIor0
LDR r1, [r0]
LDR r2, =L2DTA_IOR0
STR r1, [r2]
; I/O region(Memory controller) - 4/64KB
LDR r0, =L2DTIor1
LDR r1, [r0]
LDR r2, =L2DTA_IOR1
STR r1, [r2]
; I/O region(DMA controller) - 4/64KB
LDR r0, =L2DTIor2
LDR r1, [r0]
LDR r2, =L2DTA_IOR2
STR r1, [r2]
; I/O region(LCD controller) - 4/64KB
LDR r0, =L2DTIor3
LDR r1, [r0]
LDR r2, =L2DTA_IOR3
STR r1, [r2]
; I/O region(Ethernet MAC controller) - 4/64KB
LDR r0, =L2DTIor4
LDR r1, [r0]
LDR r2, =L2DTA_IOR4
STR r1, [r2]
; I/O region(X memory) - 32KB
LDR r0, =L2DTIor5
LDMIA r0, {r1-r8}
LDR r0, =L2DTA_IOR5
STMIA r0, {r1-r8}
; I/O region(X memory) - 32KB
LDR r0, =L2DTIor5_8
LDMIA r0, {r1-r8}
LDR r0, =L2DTA_IOR5_8
STMIA r0, {r1-r8}
; I/O region(Y memory) - 32KB
LDR r0, =L2DTIor6
LDMIA r0, {r1-r8}
LDR r0, =L2DTA_IOR6
STMIA r0, {r1-r8}
; I/O region(Y memory) - 32KB
LDR r0, =L2DTIor6_8
LDMIA r0, {r1-r8}
LDR r0, =L2DTA_IOR6_8
STMIA r0, {r1-r8}
; I/O region(P memory) - 32KB
LDR r0, =L2DTIor7
LDMIA r0, {r1-r8}
LDR r0, =L2DTA_IOR7
STMIA r0, {r1-r8}
; I/O region(P memory) - 32KB
LDR r0, =L2DTIor7_8
LDMIA r0, {r1-r8}
LDR r0, =L2DTA_IOR7_8
STMIA r0, {r1-r8}
; I/O region(AHP2APB) - 32KB
LDR r0, =L2DTIor8
LDMIA r0, {r1-r8}
LDR r0, =L2DTA_IOR8
STMIA r0, {r1-r8}
; I/O region(AHP2APB) - 32KB
LDR r0, =L2DTIor8_8
LDMIA r0, {r1-r8}
LDR r0, =L2DTA_IOR8_8
STMIA r0, {r1-r8}
; I/O region(PCMCIA register) - 64KB
LDR r0, =L2DTIor9
LDR r1, [r0]
LDR r2, =L2DTA_IOR9
STR r1, [r2]
; I/O region(PCMCIA attribute memory) - 32KB
LDR r0, =L2DTIor10
LDMIA r0, {r1-r8}
LDR r0, =L2DTA_IOR10
STMIA r0, {r1-r8}
; I/O region(PCMCIA attribute memory) - 32KB
LDR r0, =L2DTIor10_8
LDMIA r0, {r1-r8}
LDR r0, =L2DTA_IOR10_8
STMIA r0, {r1-r8}
; I/O region(Tube) - 64KB
LDR r0, =L2DTIor11
LDR r1, [r0]
LDR r2, =L2DTA_IOR11
STR r1, [r2]
; 4.Set address 0x08000000 to process identifier register
; in order to convert address 0x00000000 into 0x08000000
;LDR r1, =SDRAMBase
;MCR p15,0,r1,c13,c0,0
; 5.Enable to i_cache,d_cache,rom(read only) and mmu (0x127D)
;MRC p15,0,r1,c1,c0,0
;LDR r2, =0x127D ; data cache disable(0x1279),enable(0x127D)
;ORR r1, r1, r2
;MCR p15,0,r1,c1,c0,0
NOP
NOP
NOP
NOP
NOP
;***********************************************************
;Jump to Main program
;***********************************************************
;Change mode from supervisor mode to user mode
MOV r0, #USRmode
MSR cpsr_cf,r0
LDR sp, =USRStackOffset ; User mode stack(Internal SRAM area)
;c routin LED display
BL InitLED ; LED test
LDR r0, =0x6
BL displayLED
BL Init_Uart0 ; test printf function using with UART0
LDR r0, =Message1
BL Uart_Printf
LDR r0, =Message2
BL Uart_Printf
B .
AREA ROMData0, DATA, READONLY
;***********************************************************
;Content of descriptor tables(level1)
;Section descriptor table(1MB unit)
;***********************************************************
L1DTRom0 DCD 0x0000001A ;ROM descriptor
L1DTIsram0 DCD 0x06000C1A ;Internal SRAM descriptor (modify 5/08 for test)
L1DTSdram01 DCD 0x08000C1A ;SDRAM descriptor
DCD 0x08100C1A
DCD 0x08200C1A
DCD 0x08300C1A
DCD 0x08400C1A
DCD 0x08500C1A
DCD 0x08600C1A
DCD 0x08700C1A
L1DTSdram02 DCD 0x08800C1A
DCD 0x08900C1A
DCD 0x08A00C1A
DCD 0x08B00C1A
DCD 0x08C00C1A
DCD 0x08D00C1A
DCD 0x08E00C1A
DCD 0x08F00C1A
L1DTIor DCD 0x08F80011 ;I/O region descriptor
;**********************************************************
;Content of descriptor tables(level2)
;Small page descriptor table(4KB unit)
;**********************************************************
L2DTIor0 DCD 0x0C000FF2 ;I/O(ARM920T) descriptor
L2DTIor1 DCD 0x0C010FF2 ;I/O(memory controller) descriptor
L2DTIor2 DCD 0x0C020FF2 ;I/O(DMA controller) descriptor
L2DTIor3 DCD 0x0C030FF2 ;I/O(LCD controller) descriptor
L2DTIor4 DCD 0x0C040FF2 ;I/O(Ethernet MAC) descriptor
L2DTIor5 DCD 0x0C050FFA ;I/O(X memory) descriptor
L2DTIor5_1 DCD 0x0C051FFA
L2DTIor5_2 DCD 0x0C052FFA
L2DTIor5_3 DCD 0x0C053FFA
L2DTIor5_4 DCD 0x0C054FFA
L2DTIor5_5 DCD 0x0C055FFA
L2DTIor5_6 DCD 0x0C056FFA
L2DTIor5_7 DCD 0x0C057FFA
L2DTIor5_8 DCD 0x0C058FFA
L2DTIor5_9 DCD 0x0C059FFA
L2DTIor5_10 DCD 0x0C05AFFA
L2DTIor5_11 DCD 0x0C05BFFA
L2DTIor5_12 DCD 0x0C05CFFA
L2DTIor5_13 DCD 0x0C05DFFA
L2DTIor5_14 DCD 0x0C05EFFA
L2DTIor5_15 DCD 0x0C05FFFA
L2DTIor6 DCD 0x0C060FFA ;I/O(Y memory) descriptor
L2DTIor6_1 DCD 0x0C061FFA
L2DTIor6_2 DCD 0x0C062FFA
L2DTIor6_3 DCD 0x0C063FFA
L2DTIor6_4 DCD 0x0C064FFA
L2DTIor6_5 DCD 0x0C065FFA
L2DTIor6_6 DCD 0x0C066FFA
L2DTIor6_7 DCD 0x0C067FFA
L2DTIor6_8 DCD 0x0C068FFA
L2DTIor6_9 DCD 0x0C069FFA
L2DTIor6_10 DCD 0x0C06AFFA
L2DTIor6_11 DCD 0x0C06BFFA
L2DTIor6_12 DCD 0x0C06CFFA
L2DTIor6_13 DCD 0x0C06DFFA
L2DTIor6_14 DCD 0x0C06EFFA
L2DTIor6_15 DCD 0x0C06FFFA
L2DTIor7 DCD 0x0C070FFA ;I/O(P memory) descriptor
L2DTIor7_1 DCD 0x0C071FFA
L2DTIor7_2 DCD 0x0C072FFA
L2DTIor7_3 DCD 0x0C073FFA
L2DTIor7_4 DCD 0x0C074FFA
L2DTIor7_5 DCD 0x0C075FFA
L2DTIor7_6 DCD 0x0C076FFA
L2DTIor7_7 DCD 0x0C077FFA
L2DTIor7_8 DCD 0x0C078FFA
L2DTIor7_9 DCD 0x0C079FFA
L2DTIor7_10 DCD 0x0C07AFFA
L2DTIor7_11 DCD 0x0C07BFFA
L2DTIor7_12 DCD 0x0C07CFFA
L2DTIor7_13 DCD 0x0C07DFFA
L2DTIor7_14 DCD 0x0C07EFFA
L2DTIor7_15 DCD 0x0C07FFFA
L2DTIor8 DCD 0x0C080FF2 ;I/O(AHB2APB) descriptor
L2DTIor8_1 DCD 0x0C081FF2
L2DTIor8_2 DCD 0x0C082FF2
L2DTIor8_3 DCD 0x0C083FF2
L2DTIor8_4 DCD 0x0C084FF2
L2DTIor8_5 DCD 0x0C085FF2
L2DTIor8_6 DCD 0x0C086FF2
L2DTIor8_7 DCD 0x0C087FF2
L2DTIor8_8 DCD 0x0C088FF2
L2DTIor8_9 DCD 0x0C089FF2
L2DTIor8_10 DCD 0x0C08AFF2
L2DTIor8_11 DCD 0x0C08BFF2
L2DTIor8_12 DCD 0x0C08CFF2
L2DTIor8_13 DCD 0x0C08DFF2
L2DTIor8_14 DCD 0x0C08EFF2
L2DTIor8_15 DCD 0x0C08FFF2
L2DTIor9 DCD 0x0C090FF2 ;I/O(PCMCIA register) descriptor
L2DTIor10 DCD 0x0C0A0FFA ;I/O(PCMCIA attribute memory) descriptor
L2DTIor10_1 DCD 0x0C0A1FFA
L2DTIor10_2 DCD 0x0C0A2FFA
L2DTIor10_3 DCD 0x0C0A3FFA
L2DTIor10_4 DCD 0x0C0A4FFA
L2DTIor10_5 DCD 0x0C0A5FFA
L2DTIor10_6 DCD 0x0C0A6FFA
L2DTIor10_7 DCD 0x0C0A7FFA
L2DTIor10_8 DCD 0x0C0A8FFA
L2DTIor10_9 DCD 0x0C0A9FFA
L2DTIor10_10 DCD 0x0C0AAFFA
L2DTIor10_11 DCD 0x0C0ABFFA
L2DTIor10_12 DCD 0x0C0ACFFA
L2DTIor10_13 DCD 0x0C0ADFFA
L2DTIor10_14 DCD 0x0C0AEFFA
L2DTIor10_15 DCD 0x0C0AFFFA
L2DTIor11 DCD 0x0C0B0FF2 ;I/O(Tube) descriptor
Message1 DCB "< ROM Ver 0.1 >\n",0
Message2 DCB "Init complete!\n",0
END
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