initmn.s

Scorpio(ARM926EJ) Boot Souce program, the compiler is SDT2.51.

;************************************************************************
;   MODULE : Initmn.s                                                   *
;   PURPOSE: Startup Code(rom version)                                  *
;   VERSION: Version 0.1                                                *
;   written by CES                                                      *
;   Copyright(2000-3) samsung electoronics corp.                        *
;   12/11/2000                                                          *
;************************************************************************
        GET     lolevel.a
        GET     register.a
        GET     descript.a

        IMPORT  UNDEFHandler              ; Undefined instruction
        IMPORT  SWIHandler                ; SWI
        IMPORT  pABORTHandler             ; Prefetch abort
        IMPORT  dABORTHandler             ; Data abort
        IMPORT  IRQHandler                ; IRQ
		
        IMPORT  InitLED                   ; LED
        IMPORT  displayLED
        IMPORT  Init_Uart0                ; UART0
        IMPORT  Uart_Printf 
		
        GBLL    VECTOR
VECTOR  SETL    {TRUE}
		
        AREA	|RomStartup|, CODE, READONLY

        ENTRY

        B     RESETHandler         
        B     UNDEFHandler                ; Undefined instruction
        B     SWIHandler                  ; SWI
        B     pABORTHandler               ; Prefetch abort
        B     dABORTHandler               ; Data abort
        NOP											
        B     IRQHandler                  ; IRQ
FIQHandler
        SUB   lr, lr, #4                  ; Construct the return address 
        STMFD sp!, {lr}                   ; and push the adjusted lr_IRQ
        MRS   r14, SPSR	                  ; copy spsr_IRQ to r14
        STMFD sp!, {r0-r7, r14}           ; save work registers and spsr_IRQ
		
GetSource   
        [ :LNOT:VECTOR 
        ; read the interrupt pending status
        LDR   r1, =FIQISPR
        LDR   r1, [r1]

        MOV   r2,  #00                    ; non-vectored 
0       MOVS  r1,  r1, LSR #1
        BCS   %F1
        ADD   r2,  r2, #4
        B     %B0
        |
        LDR   r1, =FVEC_ADDR              ; semi vectored 
        LDR   r2, [r1]
        ]

1       LDR   r3,  =IntVectorTable
        ADD   r3,  r3, r2
        LDR   r3,  [r3]

        ; It is assumed that the handler function called will execute
        ; within the interrupt handler stack allocation, and the code
        ; will not manipulate the interrupt mask status, or the SPSR
        ; register:
        LDR   lr, =ReturnFromFIQService  ; generate return address
        MOV   pc, r3                     ; call handler function

UnFIQSource
ReturnFromFIQService
        LDMFD sp!, {r0-r7, r14}          ; Restore work registers and spsr_IRQ
        MSR   spsr_cf, r14
        LDMFD sp!, {pc}^                 ; return from IRQ

RESETHandler
        IMPORT  |Image$$ZI$$Base|
        IMPORT  |Image$$ZI$$Limit|
        IMPORT  |Image$$RW$$Base|
        IMPORT  |Image$$RO$$Base|
        IMPORT  |Image$$RO$$Limit|

;************************************************************************
; This routine is configuration to system registers 
;************************************************************************
SystemConfig
        ; Watch dog timer disable
        LDR   r1, =WDTMOD
        LDR   r0, =0x0
        STR   r0, [r1]

        ; Main clock setting(input:14.3MHz,output:132MHz)
        ;LDR   r1, =PLLCON
        ;LDR   r0, =0xFA31       ;FA31 14.31 -> 132
        ;LDR   r0, =0xCC55       ;CC55 14.31 -> 66
        ;STR   r0, [r1]
		
        ; CPU clock(132MHz) & Bus clock(66MHz) selecting.(PLL)
        ; CPU clock(80MHz)  & BUS clock(40MHz) selecting.(External Clock)
        MRC   p15,0,r1,c1,c0,0
;        LDR   r2, =0x40000000   ; Synchronous clock selecting
        LDR   r2, =0xC0000000   ; Asynchronous clock selectin
        ORR   r1, r1, r2
        MCR   p15,0,r1,c1,c0,0
		
        ; Set interrupt methord to interrupt controller
        [ :LNOT:VECTOR
        LDR   r2, =INTCON
        LDR   r1, [r2]
        LDR   r0, =0xB
        AND   r3, r0, r1
        STR   r3, [r2]
        |
        LDR   r2, =INTCON
        LDR   r1, [r2]
        LDR   r0, =0x4
        ORR   r3, r0, r1
        STR   r3, [r2]
        ]
		
        ;*********************************************
        ; Memory configuration.
        ; ROM: 1MB
        ; SRAM: 128KB
        ; SDRAM: 16MB
        ;*********************************************
        ; 1.ROM configuration(Bank0)
        ;   Type: AM29LV800BT(512Kx16),70ns
        ;   Bus width:16bit,Type:Normal ROM,AC:10cycle
        LDR   r0, =SMCBANK0
        LDR   r1, =0x00000201 ;901:16bit(10),902:32bit(10),101:16bit(2) 
                              ;401:16bit(5), 201:16bit(3)
        STR   r1, [r0]

        ; 2.SRAM configuration(Bank2)
        ;   Type: KM6161002A(64Kx16)
        ;   Bus width:16bit,BAS:byte,AC:3cycle
        LDR   r0, =SMCBANK2
        LDR   r1, =0x00000101 ;201 AC:3cycle, 101 AC:2cycle
        STR   r1, [r0]
	
        ; 3.SDRAM initialization 
        LDR   r0, =SDRAMCFG1
        LDR   r1, =0x8      
        STR   r1, [r0]
        LDR   r0, =SDRAMRefresh
        LDR   r1, =0xA      
        STR   r1, [r0]
		
        NOP
        NOP
        NOP
        NOP
        NOP
		
        ; *SDRAM refresh register(0x20)
        LDR   r0, =SDRAMRefresh
        LDR   r1, =0x270   ;66MHz(0x405),40MHz(0x270),33MHz(0x202),7.2MHz(0x6D)    
        STR   r1, [r0]
        ; *SDRAM config0 register(0xAF0C)
        ;  Type:KM416S4030C(1Mx16x4Bank)
        ;  Clock Target:66Mhz
        ;  CAS latency:2cycle, Row Precharge:2cycle
        ;  RAS to CAS delay:2cycle, Row cycle:6cycle(0x6A08),5cycle(0x5A08)
        LDR   r0, =SDRAMCFG0
        LDR   r1, =0x5A08      
        STR   r1, [r0]
        LDR   r0, =SDRAMCFG1
        LDR   r1, =0x10      
        STR   r1, [r0]
        LDR   r0, =SDRAMCFG1
        LDR   r1, =0x0      
        STR   r1, [r0]

        ; 4.SDRAM config1 register(0x0)
        ;   Merging write buffer enable
        LDR   r0, =SDRAMCFG1
        LDR   r1, =0x2     ;0:write buffer disable, 2: write buffer enable 
        STR   r1, [r0]
	
        ; 5.SDRAM write buffer time-out register(0x0)
        LDR   r0, =SDRAMWB
        LDR   r1, =0x0      
        STR   r1, [r0]
		
;************************************************************************
; SysInitVars: Initialise the DATA and BSS sections.
; The DATA section is initialised by copying data from the end of the
; ROM image (given by Image$$RO$$Limit) to the start of the RAM image
; (given by Image$$RW$$Base), stopping when we reach Image$$RW$$Limit.
; All data from Image$$RW$$Limit to Image$$ZI$$Limit is then cleared to 0
;************************************************************************
SysInitVars
        ; Load up the linker defined values for the static data copy
        LDR   r5, =|Image$$RO$$Limit|
        LDR   r6, =|Image$$RW$$Base|     ; and RAM copy
        LDR   r7, =|Image$$ZI$$Base|     ; zero init base -> top of initialized data
        LDR   r8, =ROMBase
		
        CMP   r5, r6                     ; Check that they are different
        BEQ   %F1
 
        ADD   r3, r8, r5
0       CMP   r6, r7                     ; copy initialized data
        LDRCC r2, [r3], #4
        STRCC r2, [r6], #4
        BCC   %B0

        ; Now initialise the  BSS area.
1       LDR   r1, =|Image$$ZI$$Limit|
        MOV   r2, #0

2       CMP   r7, r1                     ; copy zero initialized data
        STRCC r2, [r7], #4
        BCC   %B2
	   
;**************************************************************************
; Go into each mode in turn and set up the stack pointer for that mode.
; The stacks are defined in the BSS segment at the end of this file. If
; you wish to change the sizes of the stacks they should be changed there.
;**************************************************************************
SysInitStacks
        LDR   sp, =SVCStackOffset     ; SVC mode stack
        LDR   sl, =StackBase          ; No APCS_STACKGUARD space

        ; We have to set up the other privileged mode regs right now.
       
        MOV   r0, #(InterruptMask :OR: FIQmode)
        MSR   cpsr_cf,r0
        LDR   sp, =FIQStackOffset     ; FIQ mode stack

        MOV   r0, #(InterruptMask :OR: IRQmode)
        MSR   cpsr_cf,r0
        LDR   sp, =IRQStackOffset     ; IRQ mode stack

        MOV   r0, #(InterruptMask :OR: UNDmode)
        MSR   cpsr_cf,r0
        LDR   sp, =UNDStackOffset     ; Undefined instruction mode stack
        
        MOV   r0, #(InterruptMask :OR: ABTmode)
        MSR   cpsr_cf,r0
        LDR   sp, =ABTStackOffset     ; Abort mode stack
		
        ; Supervisior mode to processor mode                                               
        MOV   r0, #SVCmode
        MSR   cpsr_cf,r0

;************************************************************************
; This routine is procedure to 920T processor initialization. 
;************************************************************************
ProcConfig
        ; 1.Set base address of descriptor table 
        LDR   r0, =L1_DESC_BASE_ADDR   		
        MCR   p15,0,r0,c2,c0,0
		
        ; 2.Set domain access control register  
        LDR   r1, =0x55555555
        MCR   p15,0,r1,c3,c0,0
		
        ; 3.Store descriptor tables to memory
        ; Level1
        ; Rom MMU table descriptor(1MB)
        LDR   r0, =L1DTRom0
        LDR   r1, [r0]
        LDR   r2, =L1DTA_ROM0
        STR   r1, [r2]

        ; Internal sram MMU table descriptor(1MB)  
        LDR   r0, =L1DTIsram0
        LDR   r1, [r0]
        LDR   r2, =L1DTA_ISRAM0
        STR   r1, [r2]

        ; Sdram MMU table descriptor(8MB)  
        LDR   r0, =L1DTSdram01
        LDMIA r0, {r1-r8}
        LDR   r0, =L1DTA_SDRAM01
        STMIA r0, {r1-r8}