lolevel.a

Scorpio(ARM926EJ) Boot Souce program, the compiler is SDT2.51.

;*********************************************************
; MODULE : lolevel.a
; VERSION : Version 0.1
; written by CES
; 12/11/2000
;*********************************************************

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; Define the control bits of PSR
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; Interrupt control bits of PSR
IRQDisable      EQU     0x00000080
FIQDisable      EQU     0x00000040
InterruptMask   EQU     0x000000C0

Ibit            EQU     0x00000080
Fbit            EQU     0x00000040

; State control bit of PSR(Thumb or Arm)
Tbit            EQU     0x00000020

; Mode control bits of PSR
ModeMask        EQU     0x0000001F
USRmode	        EQU     0x00000010
SYSmode	        EQU     0x0000001F
SVCmode	        EQU     0x00000013
IRQmode	        EQU     0x00000012
FIQmode         EQU     0x00000011
ABTmode         EQU     0x00000017
UNDmode         EQU     0x0000001B

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; Target specific definitions for Scorpio
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; Scorpio memory map
; 0x00000000 ~ 0x000FFFFF : ROM(1MB)
; 0x08000000 ~ 0x08FFFFFF : RAM(16MB)
; 0x08000000 ~ 0x080FFFFF : RAM Code area(1MB)  
; 0x08100000 ~ 0x08DFFFFF : RAM Data & Heap area
; 0x08E00000 ~ 0x08EFFFFF : Video Buffer area(1MB)
; 0x08F00000 ~ 0x08F7FFFF : Preload TeakLite data area(512KB)
; 0x08F00000 ~ 0x08F3FFFF : Preload P data area(256KB)
; 0x08F40000 ~ 0x08F5FFFF : Preload X data area(128KB)
; 0x08F60000 ~ 0x08F7FFFF : Preload Y data area(128KB)
; 0x08F80000 ~ 0x08F8FFFF : L2 descriptor table area(64KB)
; 0x08F90000 ~ 0x08F9FFFF : L1 descriptor table area(64KB)
; reserved to use future to foliowing area 
; 0x08FA0000 ~ 0x08FFFFFF : stack area(384KB)
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; Internal ROM size : 1MB
ROMBase         EQU     0x00000000    ; ROM address 
ROMTop          EQU     0x000FFFFC    ; top address of ROM address

; Internal SRAM size : 8K byte(2K word)
iSRAMBase       EQU     0x06000000    ; internal SRAM base address
iSRAMTop        EQU     0x06001FFC    ; top address of interanl SRAM
eSRAMBase       EQU     0x04000000    ; external SRAM base address
SDRAMBase       EQU     0x08000000    ; SDRAM address 
SDRAMTop        EQU     0x08FFFFFC    ; top address of SDRAM address 

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; Stack pointer definition 
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; Stack base addr : 0x0600077C
; SVC stack addr  : 0x06000B7C - 0x0600077C
; FIQ stack addr  : 0x06000F7C - 0x06000B7C
; IRQ stack addr  : 0x0600137C - 0x06000B7C
; UND stack addr  : 0x0600177C - 0x0600137C
; ABT stack addr  : 0x06001B7C - 0x0600177C
; USR stack addr  : 0x06001F7C - 0x06001B7C
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; Define each mode stack size
SVCStackSize    EQU     1024
FIQStackSize    EQU     1024
IRQStackSize    EQU     1024
UNDStackSize    EQU     1024
ABTStackSize    EQU     1024
USRStackSize    EQU     1024

CombinedStackSize       EQU     (FIQStackSize+IRQStackSize+SVCStackSize+UNDStackSize+ABTStackSize+USRStackSize)
StackBase               EQU     (iSRAMTop - CombinedStackSize-(NumOfInt<<2))  ;internal SRAM area
;StackBase               EQU     (SDRAMTop - CombinedStackSize-(NumOfInt<<2))  ;SDRAM area

;All offsets are from StackBase
SVCStackLimitOffset     EQU     StackBase
SVCStackOffset          EQU     (SVCStackLimitOffset + SVCStackSize)

FIQStackLimitOffset     EQU     SVCStackOffset
FIQStackOffset          EQU     (FIQStackLimitOffset + FIQStackSize)

IRQStackLimitOffset     EQU     FIQStackOffset
IRQStackOffset          EQU     (IRQStackLimitOffset + IRQStackSize) 

UNDStackLimitOffset     EQU     IRQStackOffset
UNDStackOffset          EQU     (UNDStackLimitOffset + UNDStackSize)

ABTStackLimitOffset     EQU     UNDStackOffset
ABTStackOffset          EQU     (ABTStackLimitOffset + ABTStackSize)

USRStackLimitOffset     EQU     ABTStackOffset
USRStackOffset          EQU     (USRStackLimitOffset + USRStackSize)

;User mode stack size of application program
UserStackBase           EQU     0x8FA0000     ; only when SDRAM size is 16MB
UserStackSize           EQU     1024
UserStackOffset         EQU     (UserStackBase + UserStackSize)

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; Interrupt vector table defintion 
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NumOfInt                EQU     32

;Interrupt vector table address
IntVectorTable          EQU     iSRAMTop-(NumOfInt<<2)   ;internal SRAM area
IntVectorTableEnd       EQU     iSRAMTop
;IntVectorTable          EQU     SDRAMTop-(NumOfInt<<2)  ;SDRAM area
;IntVectorTableEnd       EQU     SDRAMTop

HandlerINT_WDT          EQU     IntVectorTable
HandlerINT_RTC          EQU     IntVectorTable+0x4
HandlerINT_TIMER0       EQU     IntVectorTable+0x8
HandlerINT_MAC          EQU     IntVectorTable+0xC     ;unused item
HandlerINT_TIMER2       EQU     IntVectorTable+0x10
HandlerINT_TIMER3       EQU     IntVectorTable+0x14
HandlerINT_EXT0         EQU     IntVectorTable+0x18
HandlerINT_USB          EQU     IntVectorTable+0x1C
HandlerINT_UART0        EQU     IntVectorTable+0x20
HandlerINT_RESV0        EQU     IntVectorTable+0x24
HandlerINT_LCDC         EQU     IntVectorTable+0x28
HandlerINT_DMA	        EQU     IntVectorTable+0x2C
HandlerINT_EXT1         EQU     IntVectorTable+0x30
HandlerINT_TIMER1       EQU     IntVectorTable+0x34
HandlerINT_PPI         	EQU     IntVectorTable+0x38
HandlerINT_EXT3       	EQU     IntVectorTable+0x3C
HandlerINT_UART1        EQU     IntVectorTable+0x40
HandlerINT_IIC          EQU     IntVectorTable+0x44
HandlerINT_COMMRX       EQU     IntVectorTable+0x48
HandlerINT_COMMTX       EQU     IntVectorTable+0x4C
HandlerINT_TEAKLITE     EQU     IntVectorTable+0x50
HandlerINT_KMI0         EQU     IntVectorTable+0x54
HandlerINT_KMI1         EQU     IntVectorTable+0x58
HandlerINT_EXT2         EQU     IntVectorTable+0x5C
HandlerINT_RESV2        EQU     IntVectorTable+0x60
HandlerINT_RESV3        EQU     IntVectorTable+0x64
HandlerINT_PCMCIA       EQU     IntVectorTable+0x68   ;unused item
HandlerINT_SMI          EQU     IntVectorTable+0x6C
HandlerINT_GPIO         EQU     IntVectorTable+0x70
HandlerINT_RESV4        EQU     IntVectorTable+0x74
HandlerINT_RESV5        EQU     IntVectorTable+0x78
HandlerINT_SSP          EQU     IntVectorTable+0x7C

; Register for remapping the memory map
ClearResetMap           EQU	    0x0C082420

; Value to mask all interrupt source
MaskAllInt              EQU	    0xFFFFFFFF

	END	; EOF lolevel_s