reg.h

Scorpio(ARM926EJ) Boot Souce program, the compiler is SDT2.51.

#define USB_R0       (volatile unsigned *)(rUSBBase+0x00)    /* Function address register */
#define USB_R1       (volatile unsigned *)(rUSBBase+0x04)    /* Power management register */
#define USB_R2       (volatile unsigned *)(rUSBBase+0x08)    /* In interrupt register bank1 */
#define USB_R4       (volatile unsigned *)(rUSBBase+0x10)    /* Out interrupt register bank1 */
#define USB_R6       (volatile unsigned *)(rUSBBase+0x18)    /* USB interrpt register */
#define USB_R7       (volatile unsigned *)(rUSBBase+0x1C)    /* In interrupt enable register bank1*/
#define USB_R9       (volatile unsigned *)(rUSBBase+0x24)    /* Out interrupt enable register bank1 */
#define USB_R11      (volatile unsigned *)(rUSBBase+0x2C)    /* USB interrupt enable register */
#define USB_R12      (volatile unsigned *)(rUSBBase+0x30)    /* Frame number1 register */
#define USB_R13      (volatile unsigned *)(rUSBBase+0x34)    /* Frame number2 register */
#define USB_R14      (volatile unsigned *)(rUSBBase+0x38)    /* Index register */
#define USB_IR1      (volatile unsigned *)(rUSBBase+0x40)    /* IN max packet register */
#define USB_IR2      (volatile unsigned *)(rUSBBase+0x44)    /* IN CSR1 register */
#define USB_IR3      (volatile unsigned *)(rUSBBase+0x48)    /* IN CSR2 register */
#define USB_OR1      (volatile unsigned *)(rUSBBase+0x4C)    /* OUT max packet register */
#define USB_OR2      (volatile unsigned *)(rUSBBase+0x50)    /* OUT CSR1 register */
#define USB_OR3      (volatile unsigned *)(rUSBBase+0x54)    /* OUT CSR2 register */
#define EP0_FIFO     (volatile unsigned *)(rUSBBase+0x80) 
#define EP1_FIFO     (volatile unsigned *)(rUSBBase+0x84) 
#define EP2_FIFO     (volatile unsigned *)(rUSBBase+0x88)
#define USB_DMAC     (volatile unsigned *)(rUSBBase+0xC0)    /* DMA enable/disable 0bit */  

/* 4.IEEE 1284(PPI)(8bit)*/
#define rPPDATA      (*(volatile unsigned *)(rPPIBase+0x00)) /* Data register */
#define rPPSTAT	     (*(volatile unsigned *)(rPPIBase+0x04)) /* status register */
#define rPPACKWTH    (*(volatile unsigned *)(rPPIBase+0x08)) /* acknowledge register */
#define rPPCON	     (*(volatile unsigned *)(rPPIBase+0x0C)) /* control register */
#define rPPINTEN     (*(volatile unsigned *)(rPPIBase+0x10)) /* enable interrupt register */
#define rPPINTPND    (*(volatile unsigned *)(rPPIBase+0x14)) /* enterrupt pending register */
#define rPPRLC	     (*(volatile unsigned *)(rPPIBase+0x18)) /* run-length count register */
#define rPPSMR	     (*(volatile unsigned *)(rPPIBase+0x1C)) /* state machine register */

/* 5.IIC register(8bit)*/
#define rIICCON	     (*(volatile unsigned *)(rIICBase+0x00)) /* control register */
#define rIICSTAT     (*(volatile unsigned *)(rIICBase+0x04)) /* status register */
#define rIICADD	     (*(volatile unsigned *)(rIICBase+0x08)) /* address register */
#define rIICDATA     (*(volatile unsigned *)(rIICBase+0x0C)) /* data register */

/* 6.TIMER register(8bit)*/
#define rTCON0       (*(volatile unsigned *)(rTIMEBase+0x00))
#define rTCON1       (*(volatile unsigned *)(rTIMEBase+0x04))
#define rTCON2       (*(volatile unsigned *)(rTIMEBase+0x08))
#define rTCON3       (*(volatile unsigned *)(rTIMEBase+0x0C))
#define rTPSR0       (*(volatile unsigned *)(rTIMEBase+0x10))
#define rTPSR1       (*(volatile unsigned *)(rTIMEBase+0x14))
#define rTPSR2       (*(volatile unsigned *)(rTIMEBase+0x18))
#define rTPSR3       (*(volatile unsigned *)(rTIMEBase+0x1C))
#define rTDR0        (*(volatile unsigned *)(rTIMEBase+0x20))
#define rTDR1        (*(volatile unsigned *)(rTIMEBase+0x24))
#define rTDR2        (*(volatile unsigned *)(rTIMEBase+0x28))
#define rTDR3        (*(volatile unsigned *)(rTIMEBase+0x2C))
#define rTCR0        (*(volatile unsigned *)(rTIMEBase+0x30))
#define rTCR1        (*(volatile unsigned *)(rTIMEBase+0x34))
#define rTCR2        (*(volatile unsigned *)(rTIMEBase+0x38))
#define rTCR3        (*(volatile unsigned *)(rTIMEBase+0x3C))

/* 7.RTC register(8bit)*/
#define rRTCCON	     (*(volatile unsigned *)(rRTCBase+0x00)) /* RTC control register */
#define rRTCRST	     (*(volatile unsigned *)(rRTCBase+0x04)) /* RTC round reset register */
#define rRTCALM	     (*(volatile unsigned *)(rRTCBase+0x08)) /* RTC alarm register */
#define rALMSEC	     (*(volatile unsigned *)(rRTCBase+0x0C)) /* Alarm second data register */
#define rALMMIN	     (*(volatile unsigned *)(rRTCBase+0x10))
#define rALMHOUR     (*(volatile unsigned *)(rRTCBase+0x14)) /* Alarm hour data register */
#define rALMDATE     (*(volatile unsigned *)(rRTCBase+0x18)) /* Alarm date data register */
#define rALMDAY	     (*(volatile unsigned *)(rRTCBase+0x1C)) /* Alarm day data register */
#define rALMMON	     (*(volatile unsigned *)(rRTCBase+0x20)) /* Alarm mon data register */
#define rALMYEAR     (*(volatile unsigned *)(rRTCBase+0x24)) /* Alarm year data register */
#define rBCDSEC	     (*(volatile unsigned *)(rRTCBase+0x28)) /* BCD second data register */
#define rBCDMIN	     (*(volatile unsigned *)(rRTCBase+0x2C)) /* BCD minute data register */
#define rBCDHOUR     (*(volatile unsigned *)(rRTCBase+0x30)) /* BCD hour data register */
#define rBCDDATE     (*(volatile unsigned *)(rRTCBase+0x34)) /* BCD day data register */
#define rBCDDAY	     (*(volatile unsigned *)(rRTCBase+0x38)) /* BCD day data register */
#define rBCDMON	     (*(volatile unsigned *)(rRTCBase+0x3C)) /* BCD month data register */
#define rBCDYEAR     (*(volatile unsigned *)(rRTCBase+0x40)) /* BCD year  data register */
#define rRTCIM       (*(volatile unsigned *)(rRTCBase+0x44)) /* BCD year  data register */
#define rRTCPEND     (*(volatile unsigned *)(rRTCBase+0x48)) /* BCD year  data register */

/* 8.Watch Dog Timer register(8bit)*/
#define rWDTMOD	     (*(volatile unsigned *)(rWDTBase+0x00)) /* Watch dog timer mode register */
#define rWDTDAT	     (*(volatile unsigned *)(rWDTBase+0x04)) /* Watch dog timer data register */
#define rWDTCNT	     (*(volatile unsigned *)(rWDTBase+0x08)) /* Watch dog timer count register */

/* 9.Programmable I/O port */
#define rGIOPCON     (*(volatile unsigned *)(rIOPBase+0x00)) /* Port direction register */
#define rGIOPDATA    (*(volatile unsigned *)(rIOPBase+0x04)) /* Data register */
#define rGIOPINTEN   (*(volatile unsigned *)(rIOPBase+0x08)) /* Interrupt enable register */
#define rGIOPLEVEL   (*(volatile unsigned *)(rIOPBase+0x0C)) /* Ative level indication register */
#define rGIOPPEND    (*(volatile unsigned *)(rIOPBase+0x10)) /* Interrupt pending register */

/* 10.Interrupt controller */
#define rINTCON      (*(volatile unsigned *)(rINTBase+0x00)) /* interrupt control register */
#define rINTPND	     (*(volatile unsigned *)(rINTBase+0x04)) /* interrupt pending register */
#define rINTMOD	     (*(volatile unsigned *)(rINTBase+0x08)) /* interrupt mode register */
#define rINTMSK	     (*(volatile unsigned *)(rINTBase+0x0C)) /* interrupt mask register */
#define rINTLEVEL    (*(volatile unsigned *)(rINTBase+0x10)) 
#define rIRQPSLV0    (*(volatile unsigned *)(rINTBase+0x14)) /* IRQ priority of slave register0 */
#define rIRQPSLV1    (*(volatile unsigned *)(rINTBase+0x18)) /* IRQ priority of slave register1 */
#define rIRQPSLV2    (*(volatile unsigned *)(rINTBase+0x1C)) /* IRQ priority of slave register2 */
#define rIRQPSLV3    (*(volatile unsigned *)(rINTBase+0x20)) /* IRQ priority of slave register3 */
#define rIRQPMST     (*(volatile unsigned *)(rINTBase+0x24)) /* IRQ priority of master register */
#define rIRQCSLV0    (*(volatile unsigned *)(rINTBase+0x28)) /* current IRQ priority of slave register0 */
#define rIRQCSLV1    (*(volatile unsigned *)(rINTBase+0x2C)) /* current IRQ priority of slave register1 */
#define rIRQCSLV2    (*(volatile unsigned *)(rINTBase+0x30)) /* current IRQ priority of slave register2 */
#define rIRQCSLV3    (*(volatile unsigned *)(rINTBase+0x34)) /* current IRQ priority of slave register3 */
#define rIRQCMST     (*(volatile unsigned *)(rINTBase+0x38)) /* current IRQ priority of master register */
#define rIRQISPR     (*(volatile unsigned *)(rINTBase+0x3C)) /* IRQ service pending register */
#define rIRQISPC     (*(volatile unsigned *)(rINTBase+0x40)) /* IRQ service clear register */
#define rFIQPSLV0    (*(volatile unsigned *)(rINTBase+0x44)) /* FIQ priority of slave register0 */
#define rFIQPSLV1    (*(volatile unsigned *)(rINTBase+0x48)) /* FIQ priority of slave register1 */
#define rFIQPSLV2    (*(volatile unsigned *)(rINTBase+0x4C)) /* FIQ priority of slave register2 */
#define rFIQPSLV3    (*(volatile unsigned *)(rINTBase+0x50)) /* FIQ priority of slave register3 */
#define rFIQPMST     (*(volatile unsigned *)(rINTBase+0x54)) /* FIQ priority of master register */
#define rFIQCSLV0    (*(volatile unsigned *)(rINTBase+0x58)) /* current FIQ priority of slave register0 */
#define rFIQCSLV1    (*(volatile unsigned *)(rINTBase+0x5C)) /* current FIQ priority of slave register1 */
#define rFIQCSLV2    (*(volatile unsigned *)(rINTBase+0x60)) /* current FIQ priority of slave register2 */
#define rFIQCSLV3    (*(volatile unsigned *)(rINTBase+0x64)) /* current FIQ priority of slave register3 */
#define rFIQCMST     (*(volatile unsigned *)(rINTBase+0x68)) /* current FIQ priority of master register */
#define rFIQISPR     (*(volatile unsigned *)(rINTBase+0x6C)) /* FIQ service pending register */
#define rFIQISPC     (*(volatile unsigned *)(rINTBase+0x70)) /* FIQ service clear register */
#define rPOLARITY    (*(volatile unsigned *)(rINTBase+0x74))
#define rIVEC_ADDR   (*(volatile unsigned *)(rINTBase+0x78))
#define rFVEC_ADDR   (*(volatile unsigned *)(rINTBase+0x78))

/* 11.SSP(prime cell) Synchronous serial port register(16bit) */
#define rSSPCR0      (*(volatile unsigned *)(rSSPBase+0x00)) /* SSP control0 register */
#define rSSPCR1      (*(volatile unsigned *)(rSSPBase+0x04)) /* SSP control1 register */
#define rSSPDR       (*(volatile unsigned *)(rSSPBase+0x08)) /* SSP data register */
#define rSSPSR       (*(volatile unsigned *)(rSSPBase+0x0C)) /* SSP status register */
#define rSSPCPSR     (*(volatile unsigned *)(rSSPBase+0x10)) /* SSP clock prescale register */
#define rSSPIIR      (*(volatile unsigned *)(rSSPBase+0x14)) /* SSP interrupt identification register */

/* 12.KMI0(prime cell) Keyboard/Mouse interface register(8bit) */
#define rKMI0CR       (*(volatile unsigned *)(rKMI0Base+0x00)) /* KMI control register */
#define rKMI0STAT     (*(volatile unsigned *)(rKMI0Base+0x04)) /* KMI status register */
#define rKMI0DATA     (*(volatile unsigned *)(rKMI0Base+0x08)) /* Tx/Rx data register */
#define rKMI0CLKDIV   (*(volatile unsigned *)(rKMI0Base+0x0C)) /* Clock divisor register */
#define rKMI0IIR      (*(volatile unsigned *)(rKMI0Base+0x10)) /* KMI interrupt register */

/* 12.KMI0(prime cell) Keyboard/Mouse interface register(8bit) */
#define rKMI1CR       (*(volatile unsigned *)(rKMI1Base+0x00)) /* KMI control register */
#define rKMI1STAT     (*(volatile unsigned *)(rKMI1Base+0x04)) /* KMI status register */
#define rKMI1DATA     (*(volatile unsigned *)(rKMI1Base+0x08)) /* Tx/Rx data register */
#define rKMI1CLKDIV   (*(volatile unsigned *)(rKMI1Base+0x0C)) /* Clock divisor register */
#define rKMI1IIR      (*(volatile unsigned *)(rKMI1Base+0x10)) /* KMI interrupt register */

/* 13.UART0(prime cell) register(8bit)*/
#define rUART0DR     (*(volatile unsigned *)(rUART0Base+0x00)) /* Rx\Tx buffer register */
#define rUART0RSR    (*(volatile unsigned *)(rUART0Base+0x04)) /* Receive status register */
#define rUART0LCR_H  (*(volatile unsigned *)(rUART0Base+0x08)) /* Line control register */
#define rUART0LCR_M  (*(volatile unsigned *)(rUART0Base+0x0C)) /* Baud rate high register */
#define rUART0LCR_L  (*(volatile unsigned *)(rUART0Base+0x10)) /* Baud rate low register */
#define rUART0CR     (*(volatile unsigned *)(rUART0Base+0x14)) /* Conrol register */
#define rUART0FR     (*(volatile unsigned *)(rUART0Base+0x18)) /* Flag register */
#define rUART0IIR    (*(volatile unsigned *)(rUART0Base+0x1C)) /* Interrupt identification register */
#define rUART0ILPR   (*(volatile unsigned *)(rUART0Base+0x20)) /* IrDA low power register */
#define rUART0_DMAC  (*(volatile unsigned *)(rUART0Base+0x24)) /* UART0 DMA Rx(0),Tx(1) enable/disable */
#define rUART0TMR    (*(volatile unsigned *)(rUART0Base+0x84)) 

/* 13.UART1(prime cell) register(8bit)*/
#define rUART1DR     (*(volatile unsigned *)(rUART1Base+0x00)) /* Rx\Tx buffer register */
#define rUART1RSR    (*(volatile unsigned *)(rUART1Base+0x04)) /* Receive status register */
#define rUART1LCR_H  (*(volatile unsigned *)(rUART1Base+0x08)) /* Line control register */
#define rUART1LCR_M  (*(volatile unsigned *)(rUART1Base+0x0C)) /* Baud rate high register */
#define rUART1LCR_L  (*(volatile unsigned *)(rUART1Base+0x10)) /* Baud rate low register */
#define rUART1CR     (*(volatile unsigned *)(rUART1Base+0x14)) /* Conrol register */
#define rUART1FR     (*(volatile unsigned *)(rUART1Base+0x18)) /* Flag register */
#define rUART1IIR    (*(volatile unsigned *)(rUART1Base+0x1C)) /* Interrupt identification register */
#define rUART1ILPR   (*(volatile unsigned *)(rUART1Base+0x20)) /* IrDA low power register */
#define rUART1_DMAC  (*(volatile unsigned *)(rUART1Base+0x24)) /* UART1 DMA Rx(0),Tx(1) enable/disable */
#define rUART1TMR    (*(volatile unsigned *)(rUART1Base+0x84)) 

/* 15.Power manager register */ 
#define rPLLCON      (*(volatile unsigned *)(rPMBase+0x00)) /* pll configuration register */
#define rMODCON      (*(volatile unsigned *)(rPMBase+0x04)) /* mode control register */
#define rHCLKCON     (*(volatile unsigned *)(rPMBase+0x08)) /* AHB clock control register */
#define rPCLKCON     (*(volatile unsigned *)(rPMBase+0x0C)) /* APB clock control register */

/* 16.Switch box register */
#define rSBCON0      (*(volatile unsigned *)(rMISCBase+0x00)) /* Switch box control0 register */
#define rSBCON1      (*(volatile unsigned *)(rMISCBase+0x04)) /* Switch box control1 register */

/* 17.Teak base register */
#define rTeakArmCtrl (*(volatile unsigned *)(rTEAKBase+0x7F0)) /* Control register */
#define rTeakArmMsg0 (*(volatile unsigned *)(rTEAKBase+0x7F4)) /* Message register0 */
#define rTeakArmMsg1 (*(volatile unsigned *)(rTEAKBase+0x7F8)) /* Message register1 */
#define rTeakArmMsg2 (*(volatile unsigned *)(rTEAKBase+0x7FC)) /* Message register2 */