reg.h

Scorpio(ARM926EJ) Boot Souce program, the compiler is SDT2.51.

/**********************************************************
 * MODULE : reg.h 
 * PURPOSE : Define the registers of each module
 * VERSION : Version 0.30
 * 2/23/2000
 * 3/28/2000
 * 4/06/2000
 * 4/07/2000
 * 5/18/2000 - miscellaneous
 * 7/07/2000 - addition KMI1
 *    before alteration
 *    KMI : 0x0C083000 ~ 0x0C0833FF
 *    MISC: 0x0C084800 ~ 0x0C084BFF
 *    after alteration
 *    KMI0: 0x0C083000 ~ 0x0C0833FF
 *    KMI1: 0x0C084800 ~ 0x0C084BFF
 *    MISC: 0x0C084C00 ~ 0x0C084FFF
 *********************************************************/

#define rSCRBase     0x40000000     /* base of the System Configuration register */
#define rASICBase    0x0C000000	    /* base of all I/O module register */
#define rPTEAKBase   0x08F00000     /* preload TeakLite base address */

/* define the base of each I/O devices */
#define rARM920T     rASICBase
#define rMEMBase     (rASICBase+0x10000) /* Memory controller */
#define rDMABase     (rASICBase+0x20000) /* DMA controller */
#define rLCDBase     (rASICBase+0x30000) /* LCD controller */
#define rEMACBase    (rASICBase+0x40000) /* Ethernet MAC controller */
#define rXMEMBase    (rASICBase+0x50000) /* TeakLite X memory(16KB) */
#define rYMEMBase    (rASICBase+0x60000) /* TeakLite Y memory(8KB) */
#define rPMEMBase    (rASICBase+0x70000) /* TeakLite P memory(32KB) */
#define rAPBBase     (rASICBase+0x80000) /* AHB2APB bridge */

/* Preload TeakLite address */
#define rPPDataArea  (rPTEAKBase+0x00)   /* preload TeakLite P data area */
#define rPXDataArea  (rPTEAKBase+0x40000)/* preload TeakLite X data area */
#define rPYDataArea  (rPTEAKBase+0x60000)/* preload TeakLite Y data area */

/************ AHB2APB bridge I/O device register *************/ 
#define rBRIDGEBase  (rAPBBase+0x000)    /* APB Bridge interface */
#define rSCIBase     (rAPBBase+0x400)    /* Smart card interface */
#define rUSBBase     (rAPBBase+0x800)    /* USB */
#define rPPIBase     (rAPBBase+0xC00)    /* IEE1284, Parallel port */
#define rIICBase     (rAPBBase+0x1000)   /* IIC */
#define rTIMEBase    (rAPBBase+0x1400)   /* Timer */
#define rRTCBase     (rAPBBase+0x1800)   /* Real time clock */
#define rWDTBase     (rAPBBase+0x1C00)   /* Watch Dog Timer */
#define rIOPBase     (rAPBBase+0x2000)   /* Programmable I/O port */
#define rRPCBase     (rAPBBase+0x2400)   /* Memory remap */ 
#define rINTBase     (rAPBBase+0x2800)   /* Interrupt controller */
#define rSSPBase     (rAPBBase+0x2C00)   /* SSP interface */
#define rKMI0Base    (rAPBBase+0x3000)   /* KMI0 */
#define rUART0Base   (rAPBBase+0x3400)   /* UART0 */
#define rUART1Base   (rAPBBase+0x3800)   /* UART1 */
#define rPMBase      (rAPBBase+0x3C00)   /* Power manager */
#define rTEAKBase    (rAPBBase+0x4000)   /* Teaklite Z space */
#define rKMI1Base    (rAPBBase+0x4800)   /* KMI1 */
#define rMISCBase    (rAPBBase+0x4C00)   /* Miscellaneous */
#define rEXT0Base    (rAPBBase+0x5000)   /* External 0 */
#define rEXT1Base    (rAPBBase+0x5400)   /* External 1 */
#define rEXT2Base    (rAPBBase+0x5800)   /* External 2 */
#define rEXT3Base    (rAPBBase+0x5C00)   /* External 3 */
#define rPCMCIABase  (rAPBBase+0x9000)   /* Programmable I/O port */

/* Memory Controller(32bit)*/
#define rSDRAMCFG0    (*(volatile unsigned *)(rMEMBase+0x00))	/* SDRAM config0 register */
#define rSDRAMCFG1    (*(volatile unsigned *)(rMEMBase+0x04))	/* SDRAM config1 register */
#define rSDRAMRefresh (*(volatile unsigned *)(rMEMBase+0x08))	/* SDRAM refresh register */
#define rSDRAMWB      (*(volatile unsigned *)(rMEMBase+0x0C))	/* SDRAM WB timeout register */
// old static memory controller version
#define rSRAMCFG      (*(volatile unsigned *)(rMEMBase+0x400))
#define rROMCFG       (*(volatile unsigned *)(rMEMBase+0x404))
#define rFLASHCFG     (*(volatile unsigned *)(rMEMBase+0x408))
#define rBANKCFG      (*(volatile unsigned *)(rMEMBase+0x40C))
// new static memory controller version
#define rSMCBANK0     (*(volatile unsigned *)(rMEMBase+0x10))
#define rSMCBANK1     (*(volatile unsigned *)(rMEMBase+0x14))
#define rSMCBANK2     (*(volatile unsigned *)(rMEMBase+0x18))
#define rSMCBANK3     (*(volatile unsigned *)(rMEMBase+0x1C))

/* DMA Controller(32bit)*/ 
// DMA control register 
#define rDMACON0     (*(volatile unsigned *)(rDMABase+0x00))	
#define rDMACON1     (*(volatile unsigned *)(rDMABase+0x40))	
#define rDMACON2     (*(volatile unsigned *)(rDMABase+0x80))	
#define rDMACON3     (*(volatile unsigned *)(rDMABase+0xC0))	
#define rDMACON4     (*(volatile unsigned *)(rDMABase+0x100))	
#define rDMACON5     (*(volatile unsigned *)(rDMABase+0x140))	

// DMA Source Start address register 
#define rDMASAR0     (*(volatile unsigned *)(rDMABase+0x04))	
#define rDMASAR1     (*(volatile unsigned *)(rDMABase+0x44))	
#define rDMASAR2     (*(volatile unsigned *)(rDMABase+0x84))	
#define rDMASAR3     (*(volatile unsigned *)(rDMABase+0xC4))	
#define rDMASAR4     (*(volatile unsigned *)(rDMABase+0x104))	
#define rDMASAR5     (*(volatile unsigned *)(rDMABase+0x144))	

// DMA Destination address register
#define rDMADAR0     (*(volatile unsigned *)(rDMABase+0x08))
#define rDMADAR1     (*(volatile unsigned *)(rDMABase+0x48))
#define rDMADAR2     (*(volatile unsigned *)(rDMABase+0x88))
#define rDMADAR3     (*(volatile unsigned *)(rDMABase+0xC8))
#define rDMADAR4     (*(volatile unsigned *)(rDMABase+0x108))
#define rDMADAR5     (*(volatile unsigned *)(rDMABase+0x148))

// DMA Terminal Counter register 
#define rDMATCR0     (*(volatile unsigned *)(rDMABase+0x0C))
#define rDMATCR1     (*(volatile unsigned *)(rDMABase+0x4C))
#define rDMATCR2     (*(volatile unsigned *)(rDMABase+0x8C))
#define rDMATCR3     (*(volatile unsigned *)(rDMABase+0xCC))
#define rDMATCR4     (*(volatile unsigned *)(rDMABase+0x10C))
#define rDMATCR5     (*(volatile unsigned *)(rDMABase+0x14C))

// DMA pending & priority register
#define rDMAPRI      (*(volatile unsigned *)(rDMABase+0x1F8))
#define rDMAPND      (*(volatile unsigned *)(rDMABase+0x1FC))

/* LCD(primecell) Controller(32bit)*/
#define rLCDTIMMING0 (*(volatile unsigned *)(rLCDBase+0x00))
#define rLCDTIMMING1 (*(volatile unsigned *)(rLCDBase+0x04))
#define rLCDTIMMING2 (*(volatile unsigned *)(rLCDBase+0x08))
#define rLCDTIMMING3 (*(volatile unsigned *)(rLCDBase+0x0C))
#define rLCDUPBASE   (*(volatile unsigned *)(rLCDBase+0x10))
#define rLCDLPBASE   (*(volatile unsigned *)(rLCDBase+0x14))
#define rLCDINTREN   (*(volatile unsigned *)(rLCDBase+0x18))
#define rLCDCONTROL  (*(volatile unsigned *)(rLCDBase+0x1C))
#define rLCDSTATUS   (*(volatile unsigned *)(rLCDBase+0x20))
#define rLCDINTR     (*(volatile unsigned *)(rLCDBase+0x24))
#define rLCDUPCUCR   (*(volatile unsigned *)(rLCDBase+0x28))
#define rLCDLPCUCR   (*(volatile unsigned *)(rLCDBase+0x2C))
#define rLCDPALBase  (rLCDBase+0x200)

/* APB Base register map */ 
/* 1.APB pulse width control register */
#define rAPBCON0     (*(volatile unsigned *)(rBRIDGEBase+0x00))
#define rAPBCON1     (*(volatile unsigned *)(rBRIDGEBase+0x04))
#define rAPBCON2     (*(volatile unsigned *)(rBRIDGEBase+0x08))
#define rAPBCON3     (*(volatile unsigned *)(rBRIDGEBase+0x0C))

/* 2.Smart card interface */
#define rSCIDATA     (*(volatile unsigned *)(rSCIBase+0x00)) 
#define rSCICR0      (*(volatile unsigned *)(rSCIBase+0x04)) 
#define rSCICR1      (*(volatile unsigned *)(rSCIBase+0x08)) 
#define rSCICR2      (*(volatile unsigned *)(rSCIBase+0x0C)) 
#define rSCIIER      (*(volatile unsigned *)(rSCIBase+0x10)) 
#define rSCIRETRY    (*(volatile unsigned *)(rSCIBase+0x14)) 
#define rSCITIDE     (*(volatile unsigned *)(rSCIBase+0x18)) 
#define rSCITXCOUNT  (*(volatile unsigned *)(rSCIBase+0x1C)) 
#define rSCIRXCOUNT  (*(volatile unsigned *)(rSCIBase+0x20)) 
#define rSCIFR       (*(volatile unsigned *)(rSCIBase+0x24))
#define rSCIRXTIME   (*(volatile unsigned *)(rSCIBase+0x28)) 
#define rSCISTAT     (*(volatile unsigned *)(rSCIBase+0x2C))
#define rSCISTABLE   (*(volatile unsigned *)(rSCIBase+0x30)) 
#define rSCIATIME    (*(volatile unsigned *)(rSCIBase+0x34)) 
#define rSCIDTIME    (*(volatile unsigned *)(rSCIBase+0x38)) 
#define rSCIATRSTIME (*(volatile unsigned *)(rSCIBase+0x3C))
#define rSCIATRDTIME (*(volatile unsigned *)(rSCIBase+0x40))
#define rSCIBLKTIME  (*(volatile unsigned *)(rSCIBase+0x44))
#define rSCICHTIME   (*(volatile unsigned *)(rSCIBase+0x48))
#define rSCICLKICC   (*(volatile unsigned *)(rSCIBase+0x4C))
#define rSCIBAUD     (*(volatile unsigned *)(rSCIBase+0x50))
#define rSCIVALUE    (*(volatile unsigned *)(rSCIBase+0x54))
#define rSCICHGUARD  (*(volatile unsigned *)(rSCIBase+0x58))
#define rSCIBLKGUARD (*(volatile unsigned *)(rSCIBase+0x5C))
#define rSCISYNCCR   (*(volatile unsigned *)(rSCIBase+0x60))
#define rSCISYNCDATA (*(volatile unsigned *)(rSCIBase+0x64))
#define rSCIRAWSTAT  (*(volatile unsigned *)(rSCIBase+0x68))
#define rSCIIIR      (*(volatile unsigned *)(rSCIBase+0x6C))
#define rSCITCR      (*(volatile unsigned *)(rSCIBase+0x80))
#define rSCITMR      (*(volatile unsigned *)(rSCIBase+0x84))
#define rSCITISR     (*(volatile unsigned *)(rSCIBase+0x88))
#define rSCITCER     (*(volatile unsigned *)(rSCIBase+0xC0))

/* 3.USB register(8bit)*/
#define rUSB_R0      (*(volatile unsigned *)(rUSBBase+0x00)) /* Function address register */
#define rUSB_R1      (*(volatile unsigned *)(rUSBBase+0x04)) /* Power management register */
#define rUSB_R14     (*(volatile unsigned *)(rUSBBase+0x38)) /* Index register */
#define rUSB_IR1     (*(volatile unsigned *)(rUSBBase+0x40)) /* IN max packet register */
#define rUSB_IR2     (*(volatile unsigned *)(rUSBBase+0x44)) /* IN CSR1 register */
#define rUSB_IR3     (*(volatile unsigned *)(rUSBBase+0x48)) /* IN CSR2 register */
#define rUSB_OR1     (*(volatile unsigned *)(rUSBBase+0x4C)) /* OUT max packet register */
#define rUSB_OR2     (*(volatile unsigned *)(rUSBBase+0x50)) /* OUT CSR1 register */
#define rUSB_OR3     (*(volatile unsigned *)(rUSBBase+0x54)) /* OUT CSR2 register */
#define rEP0_FIFO    (*(volatile unsigned *)(rUSBBase+0x80)) 
#define rEP1_FIFO    (*(volatile unsigned *)(rUSBBase+0x84))
#define rEP2_FIFO    (*(volatile unsigned *)(rUSBBase+0x78))   
#define rUSB_DMAC    (*(volatile unsigned *)(rUSBBase+0xC0)) /* DMA enable/disable 0bit */