crc_synthesis.vhd

This Circuit generates the syndrome for the CRC. This is quite useful for transmision purposes and e

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: H.38
--  \   \         Application: netgen
--  /   /         Filename: crc_synthesis.vhd
-- /___/   /\     Timestamp: Thu Jan 15 16:30:27 2009
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command: -intstyle ise -ar Structure -w -ofmt vhdl -sim crc.ngc crc_synthesis.vhd 
-- Device: xc3s400-4-ft256
-- Design Name: crc
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Verification Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity crc is
  port (
    Rst : in STD_LOGIC := 'X'; 
    reloj : in STD_LOGIC := 'X'; 
    Entrada : in STD_LOGIC := 'X'; 
    Salida : out STD_LOGIC_VECTOR ( 11 downto 0 ) 
  );
end crc;

architecture Structure of crc is
  signal E10_Dout : STD_LOGIC; 
  signal Rst_IBUF : STD_LOGIC; 
  signal reloj_BUFGP : STD_LOGIC; 
  signal Entrada_IBUF : STD_LOGIC; 
  signal E3_Dout : STD_LOGIC; 
  signal c4 : STD_LOGIC; 
  signal E2_Dout : STD_LOGIC; 
  signal c6 : STD_LOGIC; 
  signal E1_Dout : STD_LOGIC; 
  signal E5_Dout : STD_LOGIC; 
  signal E6_Dout : STD_LOGIC; 
  signal E8_Dout : STD_LOGIC; 
  signal E9_Dout : STD_LOGIC; 
  signal E11_Dout : STD_LOGIC; 
  signal E12_Dout : STD_LOGIC; 
  signal c2 : STD_LOGIC; 
  signal c15 : STD_LOGIC; 
  signal ref : STD_LOGIC; 
  signal E4_Dout : STD_LOGIC; 
  signal E7_Dout : STD_LOGIC; 
begin
  Mxor_ref_Result1 : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => Entrada_IBUF,
      I1 => E12_Dout,
      LO => ref
    );
  Salida_0_OBUF : OBUF
    port map (
      I => E1_Dout,
      O => Salida(0)
    );
  Salida_1_OBUF : OBUF
    port map (
      I => E2_Dout,
      O => Salida(1)
    );
  Mxor_c15_Result1 : LUT3_L
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => Entrada_IBUF,
      I1 => E11_Dout,
      I2 => E12_Dout,
      LO => c15
    );
  Mxor_c2_Result1 : LUT3_L
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => Entrada_IBUF,
      I1 => E1_Dout,
      I2 => E12_Dout,
      LO => c2
    );
  E12_Dout_0 : FDC
    port map (
      D => c15,
      CLR => Rst_IBUF,
      C => reloj_BUFGP,
      Q => E12_Dout
    );
  E1_Dout_1 : FDC
    port map (
      D => ref,
      CLR => Rst_IBUF,
      C => reloj_BUFGP,
      Q => E1_Dout
    );
  E2_Dout_2 : FDC
    port map (
      D => c2,
      CLR => Rst_IBUF,
      C => reloj_BUFGP,
      Q => E2_Dout
    );
  E3_Dout_3 : FDC
    port map (
      D => c4,
      CLR => Rst_IBUF,
      C => reloj_BUFGP,
      Q => E3_Dout
    );
  E4_Dout_4 : FDC
    port map (
      D => c6,
      CLR => Rst_IBUF,
      C => reloj_BUFGP,
      Q => E4_Dout
    );
  E5_Dout_5 : FDC
    port map (
      D => E4_Dout,
      CLR => Rst_IBUF,
      C => reloj_BUFGP,
      Q => E5_Dout
    );
  E6_Dout_6 : FDC
    port map (
      D => E5_Dout,
      CLR => Rst_IBUF,
      C => reloj_BUFGP,
      Q => E6_Dout
    );
  E7_Dout_7 : FDC
    port map (
      D => E6_Dout,
      CLR => Rst_IBUF,
      C => reloj_BUFGP,
      Q => E7_Dout
    );
  E8_Dout_8 : FDC
    port map (
      D => E7_Dout,
      CLR => Rst_IBUF,
      C => reloj_BUFGP,
      Q => E8_Dout
    );
  E9_Dout_9 : FDC
    port map (
      D => E8_Dout,
      CLR => Rst_IBUF,
      C => reloj_BUFGP,
      Q => E9_Dout
    );
  E10_Dout_10 : FDC
    port map (
      D => E9_Dout,
      CLR => Rst_IBUF,
      C => reloj_BUFGP,
      Q => E10_Dout
    );
  E11_Dout_11 : FDC
    port map (
      D => E10_Dout,
      CLR => Rst_IBUF,
      C => reloj_BUFGP,
      Q => E11_Dout
    );
  Mxor_c6_Result1 : LUT3_L
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => Entrada_IBUF,
      I1 => E3_Dout,
      I2 => E12_Dout,
      LO => c6
    );
  Mxor_c4_Result1 : LUT3_L
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => Entrada_IBUF,
      I1 => E2_Dout,
      I2 => E12_Dout,
      LO => c4
    );
  reloj_BUFGP_12 : BUFGP
    port map (
      I => reloj,
      O => reloj_BUFGP
    );
  Rst_IBUF_13 : IBUF
    port map (
      I => Rst,
      O => Rst_IBUF
    );
  Entrada_IBUF_14 : IBUF
    port map (
      I => Entrada,
      O => Entrada_IBUF
    );
  Salida_11_OBUF : OBUF
    port map (
      I => E12_Dout,
      O => Salida(11)
    );
  Salida_10_OBUF : OBUF
    port map (
      I => E11_Dout,
      O => Salida(10)
    );
  Salida_9_OBUF : OBUF
    port map (
      I => E10_Dout,
      O => Salida(9)
    );
  Salida_8_OBUF : OBUF
    port map (
      I => E9_Dout,
      O => Salida(8)
    );
  Salida_7_OBUF : OBUF
    port map (
      I => E8_Dout,
      O => Salida(7)
    );
  Salida_6_OBUF : OBUF
    port map (
      I => E7_Dout,
      O => Salida(6)
    );
  Salida_5_OBUF : OBUF
    port map (
      I => E6_Dout,
      O => Salida(5)
    );
  Salida_4_OBUF : OBUF
    port map (
      I => E5_Dout,
      O => Salida(4)
    );
  Salida_3_OBUF : OBUF
    port map (
      I => E4_Dout,
      O => Salida(3)
    );
  Salida_2_OBUF : OBUF
    port map (
      I => E3_Dout,
      O => Salida(2)
    );

end Structure;