crc.vhd

来自「This Circuit generates the syndrome for 」· VHDL 代码 · 共 75 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CRC is
    Port ( Entrada : in std_logic;
           reloj : in std_logic;
			  Rst : in std_logic;
			  Salida : out std_logic_vector(11 DOWNTO 0) );
end CRC;

architecture Behavioral of CRC is

--Llamamos al componente TipoD
component TipoD
    Port ( Rset : in std_logic;
           Din : in std_logic;
           clk : in std_logic;
           Dout : out std_logic);
end component;

--Declaramos las se馻les que interconectaran los componentes
signal ref: std_logic;
signal c1: std_logic;
signal c2: std_logic;
signal c3: std_logic;
signal c4: std_logic;
signal c5: std_logic;
signal c6: std_logic;
signal c7: std_logic;
signal c8: std_logic;
signal c9: std_logic;
signal c10: std_logic;
signal c11: std_logic;
signal c12: std_logic;
signal c13: std_logic;
signal c14: std_logic;
signal c15: std_logic;
signal c16: std_logic;

begin
	
	--Declaramos los componentes
	E1 : TipoD port map(Rst, ref, reloj, c1);
	E2 : TipoD port map(Rst, c2, reloj, c3);
	E3 : TipoD port map(Rst, c4, reloj, c5);
	E4 : TipoD port map(Rst, c6, reloj, c7);
	E5 : TipoD port map(Rst, c7, reloj, c8);
	E6 : TipoD port map(Rst, c8, reloj, c9);
	E7 : TipoD port map(Rst, c9, reloj, c10);
	E8 : TipoD port map(Rst, c10, reloj, c11);
	E9 : TipoD port map(Rst, c11, reloj, c12);
	E10 : TipoD port map(Rst, c12, reloj, c13);
	E11 : TipoD port map(Rst, c13, reloj, c14);
	E12 : TipoD port map(Rst, c15, reloj, c16);
	c2 <= c1 xor ref;
	c4 <= c3 xor ref;
	c6 <= c5 xor ref;
	c15 <= c14 xor ref;
	ref <= c16 xor Entrada; 
	Salida(0) <= c1;
	Salida(1) <= c3;
	Salida(2) <= c5;
	Salida(3) <= c7;
	Salida(4) <= c8;
	Salida(5) <= c9;
	Salida(6) <= c10;
	Salida(7) <= c11;
	Salida(8) <= c12;
	Salida(9) <= c13;
	Salida(10) <= c14;
	Salida(11) <= c16;
	
	--process (clk,)	 A馻dir una se馻l que se pone a uno cuando la transmision ok.

end Behavioral;