tipod.twr

来自「This Circuit generates the syndrome for 」· TWR 代码 · 共 51 行

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Release 7.1.04i Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

C:/XilinxISE71/bin/nt/trce.exe -ise e:\practica uno\P1_CRC_gen.ise -intstyle
ise -e 3 -l 3 -s 4 -xml tipod tipod.ncd -o tipod.twr tipod.pcf


Design file:              tipod.ncd
Physical constraint file: tipod.pcf
Device,speed:             xc3s400,-4 (PRODUCTION 1.37 2005-07-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
Din         |   -0.156(R)|    1.569(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
Dout        |    7.382(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Analysis completed Thu Oct 30 13:22:55 2008
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Peak Memory Usage: 82 MB