prueba.vhd

This Circuit generates the syndrome for the CRC. This is quite useful for transmision purposes and e

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-- Company: 
-- Engineer:
--
-- Create Date:   14:20:02 10/23/2008
-- Design Name:   crc
-- Module Name:   Prueba.vhd
-- Project Name:  P1_CRC_gen
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: crc
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY Prueba_vhd IS
END Prueba_vhd;

ARCHITECTURE behavior OF Prueba_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT crc
	PORT(
		Entrada : IN std_logic;
		reloj : IN std_logic;
		Rst : IN std_logic;          
		Salida : OUT std_logic_vector( 11 downto 0 )
		);
	END COMPONENT;

	--Inputs
	SIGNAL Entrada :  std_logic := '0';
	SIGNAL reloj :  std_logic := '0';
	SIGNAL Rst :  std_logic := '1';

	--Outputs
	SIGNAL Salida :  std_logic_vector( 11 downto 0 );

	constant periodo: time := 100 ns;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: crc PORT MAP(
		Entrada => Entrada,
		reloj => reloj,
		Rst => Rst,
		Salida => Salida
	);

	reloj <= not reloj after periodo/2;

	tb : PROCESS
	BEGIN
		
		Rst <= '1';
		wait for periodo;
		Rst <= '0';
		Entrada <= '1';
		wait for periodo;
		Entrada <= '0';
		wait for periodo;
		Entrada <= '0';
		wait for periodo;
		Entrada <= '1';
		wait for periodo;
		Entrada <= '0';
		wait for periodo;
		Entrada <= '0';
		wait for periodo;
		Entrada <= '0';
		wait for periodo;
		Entrada <= '0';
		wait for periodo;
		Entrada <= '0';
		wait for periodo;
		Entrada <= '0';
		wait for periodo;
		Entrada <= '0';
		wait for periodo;
		Entrada <= '1';
		wait for periodo;
		Entrada <= '0';
		wait for periodo;
		Entrada <= '0';
		wait for periodo;
		Entrada <= '1';
		wait for periodo;
		Entrada <= '0';
		wait for periodo;
		Entrada <= '0';
		wait for periodo;
		Entrada <= '0';
		wait for periodo;
		Entrada <= '1';
		wait for periodo;
		Entrada <= '0';
		wait for periodo;
		Entrada <= '1';
		wait for periodo;
		Entrada <= '1';
		wait for periodo;
		Entrada <= '0';
		wait for periodo;
		Entrada <= '1';
--		wait for periodo;
--		Entrada <= salida(9);
--		wait for periodo;
--		Entrada <= salida(10);
--		wait for periodo;
--		Entrada <= salida(11);
		wait; 
	END PROCESS;

END;