__projnav.log

This Circuit generates the syndrome for the CRC. This is quite useful for transmision purposes and e

Selected Device : 3s400ft256-4 

 Number of Slices:                       7  out of   3584     0%  
 Number of Slice Flip Flops:            12  out of   7168     0%  
 Number of 4 input LUTs:                 5  out of   7168     0%  
 Number of bonded IOBs:                 15  out of    173     8%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
reloj                              | BUFGP                  | 12    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 2.672ns (Maximum Frequency: 374.252MHz)
   Minimum input arrival time before clock: 2.835ns
   Maximum output required time after clock: 7.367ns
   Maximum combinational path delay: No path found

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd "c:\documents and
settings\administrador\mis documentos\teleco files\4 teleco\1er
cuatrimestre\arquitectura de computadores [9][ac]\practicas\practica 1 generador
crc/_ngo" -i -p xc3s400-ft256-4 crc.ngc crc.ngd 

Reading NGO file 'C:/Documents and Settings/Administrador/Mis documentos/Teleco
Files/4 Teleco/1ER CUATRIMESTRE/Arquitectura de Computadores
[9][AC]/Practicas/Practica 1 Generador CRC/crc.ngc' ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "crc.ngd" ...

Writing NGDBUILD log file "crc.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s400ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:          12 out of   7,168    1%
  Number of 4 input LUTs:               5 out of   7,168    1%
Logic Distribution:
  Number of occupied Slices:                           10 out of   3,584    1%
    Number of Slices containing only related logic:      10 out of      10  100%
    Number of Slices containing unrelated logic:          0 out of      10    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:           5 out of   7,168    1%
  Number of bonded IOBs:               15 out of     173    8%
  Number of GCLKs:                     1 out of       8   12%

Total equivalent gate count for design:  129
Additional JTAG gate count for IOBs:  720
Peak Memory Usage:  109 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "crc_map.mrp" for details.




Started process "Place & Route".




Constraints file: crc.pcf.
Loading device for application Rf_Device from file '3s400.nph' in environment
C:/Xilinx.
   "crc" is an NCD, version 3.1, device xc3s400, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  1 out of 8      12%
   Number of External IOBs            15 out of 173     8%
      Number of LOCed IOBs             0 out of 15      0%

   Number of Slices                   10 out of 3584    1%
      Number of SLICEMs                0 out of 1792    0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:9896cd) REAL time: 1 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 1 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs 

Phase 6.8
.
Phase 6.8 (Checksum:9933a5) REAL time: 1 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 1 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 1 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 1 secs 

Writing design to file crc.ncd


Total REAL time to Placer completion: 1 secs 
Total CPU time to Placer completion: 1 secs 

Starting Router

Phase 1: 55 unrouted;       REAL time: 2 secs 

Phase 2: 44 unrouted;       REAL time: 2 secs 

Phase 3: 6 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 


Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|         reloj_BUFGP |      BUFGMUX3| No   |   10 |  0.019     |  1.033      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  76 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file crc.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s400.nph' in environment
C:/Xilinx.
   "crc" is an NCD, version 3.1, device xc3s400, package ft256, speed -4

Analysis completed Sat Jan 10 18:24:26 2009
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 2 secs 




Started process "Generate Post-Place & Route Simulation Model".

INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx SIMPRIM
   simulation primitives and has to be used with SIMPRIM library for correct
   compilation and simulation. 





Project Navigator Auto-Make Log File
-------------------------------------




Started process "Compile HDL Simulation Libraries".

XILINX = 'C:\Xilinx'
Library Source => 'C:\Xilinx'

Compilation Mode = FAST
Scheduling library compilation for SPARTAN-3 
Compiling Xilinx HDL Libraries for ModelSim PE Simulator
Language => vhdl
Backing up setup files if any...
Output directory => 'C:\Xilinx\vhdl\mti_pe'

--> Compiling vhdl unisim library
    > Unisim compiled to C:\Xilinx\vhdl\mti_pe\unisim
    > Log file C:\Xilinx\vhdl\mti_pe\unisim\cxl_unisim.log generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[unisim]: No error(s), no warning(s)

--> Compiling vhdl simprim library
    > Simprim compiled to C:\Xilinx\vhdl\mti_pe\simprim
    > Log file C:\Xilinx\vhdl\mti_pe\simprim\cxl_simprim.log generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[simprim]: No error(s), 49 warning(s)

--> Compiling vhdl XilinxCoreLib library

Process interrupted by the user.
ERROR: compxlib failed
Process "Compile HDL Simulation Libraries" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Compile HDL Simulation Libraries".

XILINX = 'C:\Xilinx'
Library Source => 'C:\Xilinx'

Compilation Mode = FAST
Scheduling library compilation for SPARTAN-3 
Compiling Xilinx HDL Libraries for ModelSim SE Simulator
Language => vhdl
Backing up setup files if any...
Output directory => 'C:\Xilinx\vhdl\mti_se'

--> Compiling vhdl unisim library
    > Unisim compiled to C:\Xilinx\vhdl\mti_se\unisim
    > Log file C:\Xilinx\vhdl\mti_se\unisim\cxl_unisim.log generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[unisim]: No error(s), no warning(s)

--> Compiling vhdl simprim library
    > Simprim compiled to C:\Xilinx\vhdl\mti_se\simprim
    > Log file C:\Xilinx\vhdl\mti_se\simprim\cxl_simprim.log generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[simprim]: No error(s), 49 warning(s)

--> Compiling vhdl XilinxCoreLib library
    > XilinxCoreLib compiled to C:\Xilinx\vhdl\mti_se\XilinxCoreLib
    > Log file C:\Xilinx\vhdl\mti_se\XilinxCoreLib\cxl_XilinxCoreLib.log generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[XilinxCoreLib]: No error(s), 55 warning(s)

Log file (compxlib.log) generated.



Project Navigator Auto-Make Log File
-------------------------------------



Loading device for application Rf_Device from file '3s400.nph' in environment
C:/Xilinx.
Loading device for application Rf_Device from file '3s400.nph' in environment
C:/Xilinx.
   "crc" is an NCD, version 3.1, device xc3s400, package ft256, speed -4
   "crc" is an NCD, version 3.1, device xc3s400, package ft256, speed -4
Design load 35% complete
INFO:
--------------------------------------------------------------
The power estimate will be calculated using ADVANCED data.
--------------------------------------------------------------

Design load 35% complete
INFO:
--------------------------------------------------------------
The power estimate will be calculated using ADVANCED data.
--------------------------------------------------------------

Design load 50% complete
Design load 50% completeDesign load 66% completeDesign load 81% completeDesign load 85% completeDesign load 98% complete
Design load 66% completeDesign load 81% completeDesign load 85% completeDesign load 98% complete
Design load 100% complete
XPower and Datasheet may have some Quiescent Current differences.
This is due to the fact that the quiescent numbers in XPower are based on
measurements of real designs with active functional elements reflecting real
world design scenarios.

Design load 100% complete
XPower and Datasheet may have some Quiescent Current differences.
This is due to the fact that the quiescent numbers in XPower are based on
measurements of real designs with active functional elements reflecting real
world design scenarios.

WARNING:PowerEstimator:127 - Power estimate is considered inaccurate. To see
   details, generate an advanced report with the "-v -a" switch.
WARNING:Power:760 - Only 0% of the register output signals have been set.
WARNING:Power:762 - Only 0% of the design signals have been set.
WARNING:Power:763 - Only 0% of the design signals toggle.
----------------------------------------------------------------
Release 7.1i - XPower SoftwareVersion:H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Design:       crc.ncd
Preferences:  crc.pcf
Part:         3s400ft256-4
Data version: ADVANCED,v1.0,11-03-03

XPower and Datasheet may have some Quiescent Current differences.
This is due to the fact that the quiescent numbers in XPower are based on
measurements of real designs with active functional elements reflecting real
world design scenarios.



Power summary:                        I(mA)    P(mW)
----------------------------------------------------------------
Total estimated power consumption:                92
                               ---
                      Vccint 1.20V:       35       42
                      Vccaux 2.50V:       20       50
                      Vcco25 2.50V:        0        0
                               ---