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This Circuit generates the syndrome for the CRC. This is quite useful for transmision purposes and e

Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:989689) REAL time: 1 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs 

Phase 3.2



Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 1 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs 

Phase 6.8
Phase 6.8 (Checksum:98989b) REAL time: 1 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 1 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 1 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 1 secs 

Writing design to file tipod.ncd


Total REAL time to Placer completion: 1 secs 
Total CPU time to Placer completion: 1 secs 

Starting Router

Phase 1: 5 unrouted;       REAL time: 1 secs 

Phase 2: 3 unrouted;       REAL time: 1 secs 

Phase 3: 0 unrouted;       REAL time: 1 secs 

Phase 4: 0 unrouted;       REAL time: 1 secs 


Total REAL time to Router completion: 1 secs 
Total CPU time to Router completion: 1 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      BUFGMUX7| No   |    1 |  0.000     |  1.073      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  74 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file tipod.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s400.nph' in environment
C:/XilinxISE71.
   "tipod" is an NCD, version 3.1, device xc3s400, package ft256, speed -4

Analysis completed Thu Oct 30 13:22:55 2008
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 1 secs 


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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/CRC is now defined in a different file: was E:/Pdos/CRC.vhd, now is E:/Practica Uno/CRC.vhd
WARNING:HDLParsers:3215 - Unit work/CRC/BEHAVIORAL is now defined in a different file: was E:/Pdos/CRC.vhd, now is E:/Practica Uno/CRC.vhd
WARNING:HDLParsers:3215 - Unit work/TIPOD is now defined in a different file: was E:/Pdos/TipoD.vhd, now is E:/Practica Uno/TipoD.vhd
WARNING:HDLParsers:3215 - Unit work/TIPOD/BEHAVIORAL is now defined in a different file: was E:/Pdos/TipoD.vhd, now is E:/Practica Uno/TipoD.vhd
Compiling vhdl file "E:/Practica Uno/TipoD.vhd" in Library work.
Architecture behavioral of Entity tipod is up to date.
Compiling vhdl file "E:/Practica Uno/CRC.vhd" in Library work.
ERROR:HDLParsers:164 - "E:/Practica Uno/CRC.vhd" Line 8. parse error, unexpected END, expecting IDENTIFIER
--> 

Total memory usage is 75400 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    4 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/Practica Uno/TipoD.vhd" in Library work.
Architecture behavioral of Entity tipod is up to date.
Compiling vhdl file "E:/Practica Uno/CRC.vhd" in Library work.
ERROR:HDLParsers:164 - "E:/Practica Uno/CRC.vhd" Line 8. parse error, unexpected CLOSEPAR, expecting IDENTIFIER
--> 

Total memory usage is 75400 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/Practica Uno/TipoD.vhd" in Library work.
Architecture behavioral of Entity tipod is up to date.
Compiling vhdl file "E:/Practica Uno/CRC.vhd" in Library work.
Entity <crc> compiled.
Entity <crc> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <crc> (Architecture <behavioral>).
Entity <crc> analyzed. Unit <crc> generated.

Analyzing Entity <TipoD> (Architecture <behavioral>).
Entity <TipoD> analyzed. Unit <TipoD> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <TipoD>.
    Related source file is "E:/Practica Uno/TipoD.vhd".
    Found 1-bit register for signal <Dout>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <TipoD> synthesized.


Synthesizing Unit <crc>.
    Related source file is "E:/Practica Uno/CRC.vhd".
WARNING:Xst:1306 - Output <sindrome> is never assigned.
    Found 1-bit xor2 for signal <c15>.
    Found 1-bit xor2 for signal <c2>.
    Found 1-bit xor2 for signal <c4>.
    Found 1-bit xor2 for signal <c6>.
    Found 1-bit xor2 for signal <ref>.
Unit <crc> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
WARNING:Xst:524 - All outputs of the instance <E1> of the block <TipoD> are unconnected in block <crc>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <E2> of the block <TipoD> are unconnected in block <crc>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <E3> of the block <TipoD> are unconnected in block <crc>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <E4> of the block <TipoD> are unconnected in block <crc>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <E5> of the block <TipoD> are unconnected in block <crc>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <E6> of the block <TipoD> are unconnected in block <crc>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <E7> of the block <TipoD> are unconnected in block <crc>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <E8> of the block <TipoD> are unconnected in block <crc>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <E9> of the block <TipoD> are unconnected in block <crc>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <E10> of the block <TipoD> are unconnected in block <crc>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <E11> of the block <TipoD> are unconnected in block <crc>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <E12> of the block <TipoD> are unconnected in block <crc>.
   This instance will be removed from the design along with all underlying logic
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <crc> ...
Loading device for application Rf_Device from file '3s400.nph' in environment C:/XilinxISE71.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block crc, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400ft256-4 

 Number of bonded IOBs:                 15  out of    173     8%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found

=========================================================================


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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/Practica Uno/TipoD.vhd" in Library work.
Architecture behavioral of Entity tipod is up to date.
Compiling vhdl file "E:/Practica Uno/CRC.vhd" in Library work.
Entity <crc> compiled.
Entity <crc> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <crc> (Architecture <behavioral>).
Entity <crc> analyzed. Unit <crc> generated.

Analyzing Entity <TipoD> (Architecture <behavioral>).
Entity <TipoD> analyzed. Unit <TipoD> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <TipoD>.
    Related source file is "E:/Practica Uno/TipoD.vhd".
    Found 1-bit register for signal <Dout>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <TipoD> synthesized.


Synthesizing Unit <crc>.
    Related source file is "E:/Practica Uno/CRC.vhd".
    Found 1-bit xor2 for signal <c15>.
    Found 1-bit xor2 for signal <c2>.
    Found 1-bit xor2 for signal <c4>.
    Found 1-bit xor2 for signal <c6>.
    Found 1-bit xor2 for signal <ref>.
Unit <crc> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 12
 1-bit register                    : 12
# Xors                             : 5
 1-bit xor2                        : 5

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <crc> ...
Loading device for application Rf_Device from file '3s400.nph' in environment C:/XilinxISE71.

Mapping all equations...
Building and optimizing final netlist ...