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Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "E:/Pdos/TipoD.vhd" in Library work.Entity <TipoD> compiled.Entity <TipoD> (Architecture <Behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <tipod> (Architecture <Behavioral>).Entity <tipod> analyzed. Unit <tipod> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <tipod>. Related source file is "E:/Pdos/TipoD.vhd". Found 1-bit register for signal <Dout>. Summary: inferred 1 D-type flip-flop(s).Unit <tipod> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 1 1-bit register : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <tipod> ...Loading device for application Rf_Device from file '3s400.nph' in environment C:/XilinxISE71.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block tipod, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s400ft256-4 Number of Slices: 1 out of 3584 0% Number of Slice Flip Flops: 1 out of 7168 0% Number of bonded IOBs: 4 out of 173 2% Number of GCLKs: 1 out of 8 12% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 1 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: 1.825ns Maximum output required time after clock: 7.165ns Maximum combinational path delay: No path found=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "E:/Pdos/CRC.vhd" in Library work.Entity <CRC> compiled.ERROR:HDLParsers:164 - "E:/Pdos/CRC.vhd" Line 39. parse error, unexpected IDENTIFIER, expecting OPENPAR or TICK or LSQBRACKERROR:HDLParsers:164 - "E:/Pdos/CRC.vhd" Line 40. parse error, unexpected IDENTIFIER, expecting OPENPAR or TICK or LSQBRACKERROR:HDLParsers:164 - "E:/Pdos/CRC.vhd" Line 41. parse error, unexpected IDENTIFIER, expecting OPENPAR or TICK or LSQBRACKERROR:HDLParsers:164 - "E:/Pdos/CRC.vhd" Line 42. parse error, unexpected IDENTIFIER, expecting OPENPAR or TICK or LSQBRACKERROR:HDLParsers:164 - "E:/Pdos/CRC.vhd" Line 43. parse error, unexpected IDENTIFIER, expecting OPENPAR or TICK or LSQBRACKERROR:HDLParsers:164 - "E:/Pdos/CRC.vhd" Line 44. parse error, unexpected IDENTIFIER, expecting OPENPAR or TICK or LSQBRACKERROR:HDLParsers:164 - "E:/Pdos/CRC.vhd" Line 45. parse error, unexpected IDENTIFIER, expecting OPENPAR or TICK or LSQBRACKERROR:HDLParsers:164 - "E:/Pdos/CRC.vhd" Line 46. parse error, unexpected IDENTIFIER, expecting OPENPAR or TICK or LSQBRACKERROR:HDLParsers:164 - "E:/Pdos/CRC.vhd" Line 47. parse error, unexpected IDENTIFIER, expecting OPENPAR or TICK or LSQBRACKERROR:HDLParsers:164 - "E:/Pdos/CRC.vhd" Line 48. parse error, unexpected IDENTIFIER, expecting OPENPAR or TICK or LSQBRACKERROR:HDLParsers:164 - "E:/Pdos/CRC.vhd" Line 49. parse error, unexpected IDENTIFIER, expecting OPENPAR or TICK or LSQBRACKERROR:HDLParsers:164 - "E:/Pdos/CRC.vhd" Line 50. parse error, unexpected IDENTIFIER, expecting OPENPAR or TICK or LSQBRACK--> Total memory usage is 75400 kilobytesNumber of errors : 12 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "E:/Pdos/TipoD.vhd" in Library work.Architecture behavioral of Entity tipod is up to date.Compiling vhdl file "E:/Pdos/CRC.vhd" in Library work.Entity <crc> compiled.Entity <CRC> (Architecture <Behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <crc> (Architecture <Behavioral>).Entity <crc> analyzed. Unit <crc> generated.Analyzing Entity <TipoD> (Architecture <behavioral>).Entity <TipoD> analyzed. Unit <TipoD> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <TipoD>. Related source file is "E:/Pdos/TipoD.vhd". Found 1-bit register for signal <Dout>. Summary: inferred 1 D-type flip-flop(s).Unit <TipoD> synthesized.Synthesizing Unit <crc>. Related source file is "E:/Pdos/CRC.vhd".WARNING:Xst:1306 - Output <Salida> is never assigned. Found 1-bit xor2 for signal <c15>. Found 1-bit xor2 for signal <c2>. Found 1-bit xor2 for signal <c4>. Found 1-bit xor2 for signal <c6>. Found 1-bit xor2 for signal <ref>.Unit <crc> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...WARNING:Xst:524 - All outputs of the instance <E1> of the block <TipoD> are unconnected in block <crc>. This instance will be removed from the design along with all underlying logicWARNING:Xst:524 - All outputs of the instance <E2> of the block <TipoD> are unconnected in block <crc>. This instance will be removed from the design along with all underlying logicWARNING:Xst:524 - All outputs of the instance <E3> of the block <TipoD> are unconnected in block <crc>. This instance will be removed from the design along with all underlying logicWARNING:Xst:524 - All outputs of the instance <E4> of the block <TipoD> are unconnected in block <crc>. This instance will be removed from the design along with all underlying logicWARNING:Xst:524 - All outputs of the instance <E5> of the block <TipoD> are unconnected in block <crc>. This instance will be removed from the design along with all underlying logicWARNING:Xst:524 - All outputs of the instance <E6> of the block <TipoD> are unconnected in block <crc>. This instance will be removed from the design along with all underlying logicWARNING:Xst:524 - All outputs of the instance <E7> of the block <TipoD> are unconnected in block <crc>. This instance will be removed from the design along with all underlying logicWARNING:Xst:524 - All outputs of the instance <E8> of the block <TipoD> are unconnected in block <crc>. This instance will be removed from the design along with all underlying logicWARNING:Xst:524 - All outputs of the instance <E9> of the block <TipoD> are unconnected in block <crc>. This instance will be removed from the design along with all underlying logicWARNING:Xst:524 - All outputs of the instance <E10> of the block <TipoD> are unconnected in block <crc>. This instance will be removed from the design along with all underlying logicWARNING:Xst:524 - All outputs of the instance <E11> of the block <TipoD> are unconnected in block <crc>. This instance will be removed from the design along with all underlying logicWARNING:Xst:524 - All outputs of the instance <E12> of the block <TipoD> are unconnected in block <crc>. This instance will be removed from the design along with all underlying logicDynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <crc> ...Loading device for application Rf_Device from file '3s400.nph' in environment C:/XilinxISE71.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block crc, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s400ft256-4 Number of bonded IOBs: 4 out of 173 2% =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: No path found=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Compiling vhdl file "E:/Pdos/TipoD.vhd" in Library work.Entity <TipoD> compiled.Entity <TipoD> (Architecture <Behavioral>) compiled.Compiling vhdl file "E:/Pdos/CRC.vhd" in Library work.Entity <CRC> compiled.Entity <CRC> (Architecture <Behavioral>) compiled.tdtfi(vhdl) completed successfully.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd "e:\practica uno/_ngo" -nt timestamp -i-p xc3s400-ft256-4 tipod.ngc tipod.ngd Reading NGO file 'E:/Practica Uno/tipod.ngc' ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "tipod.ngd" ...Writing NGDBUILD log file "tipod.bld"...NGDBUILD done.
Started process "Map".Using target part "3s400ft256-4".Mapping design into LUTs...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary:Number of errors: 0Number of warnings: 0Logic Utilization:Logic Distribution: Number of Slices containing only related logic: 0 out of 0 0% Number of Slices containing unrelated logic: 0 out of 0 0% *See NOTES below for an explanation of the effects of unrelated logic Number of bonded IOBs: 4 out of 173 2% IOB Flip Flops: 1 Number of GCLKs: 1 out of 8 12%Total equivalent gate count for design: 11Additional JTAG gate count for IOBs: 192Peak Memory Usage: 107 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Mapping completed.See MAP report file "tipod_map.mrp" for details.
Started process "Place & Route".Constraints file: tipod.pcf.Loading device for application Rf_Device from file '3s400.nph' in environmentC:/XilinxISE71. "tipod" is an NCD, version 3.1, device xc3s400, package ft256, speed -4Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000Celsius)Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)Device speed data version: "PRODUCTION 1.37 2005-07-22".Device Utilization Summary: Number of BUFGMUXs 1 out of 8 12% Number of External IOBs 4 out of 173 2% Number of LOCed IOBs 0 out of 4 0%Overall effort level (-ol): Standard (set by user)Placer effort level (-pl): Standard (set by user)Placer cost table entry (-t): 1⌨️ 快捷键说明
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