crc.twr

This Circuit generates the syndrome for the CRC. This is quite useful for transmision purposes and e

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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -ise
c:\documents and settings\administrador\mis documentos\teleco files\4 teleco\1er cuatrimestre\arquitectura de computadores [9][ac]\practicas\practica 1 generador crc\P1_CRC_gen.ise
-intstyle ise -e 3 -l 3 -s 4 -xml crc crc.ncd -o crc.twr crc.pcf


Design file:              crc.ncd
Physical constraint file: crc.pcf
Device,speed:             xc3s400,-4 (PRODUCTION 1.35 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock reloj
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
Entrada     |    1.143(R)|    1.079(R)|reloj_BUFGP       |   0.000|
------------+------------+------------+------------------+--------+

Clock reloj to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
Salida<0>   |    9.492(R)|reloj_BUFGP       |   0.000|
Salida<10>  |    9.719(R)|reloj_BUFGP       |   0.000|
Salida<11>  |    9.087(R)|reloj_BUFGP       |   0.000|
Salida<1>   |    8.800(R)|reloj_BUFGP       |   0.000|
Salida<2>   |    9.148(R)|reloj_BUFGP       |   0.000|
Salida<3>   |    9.507(R)|reloj_BUFGP       |   0.000|
Salida<4>   |   11.036(R)|reloj_BUFGP       |   0.000|
Salida<5>   |   10.655(R)|reloj_BUFGP       |   0.000|
Salida<6>   |   10.149(R)|reloj_BUFGP       |   0.000|
Salida<7>   |    9.388(R)|reloj_BUFGP       |   0.000|
Salida<8>   |   10.071(R)|reloj_BUFGP       |   0.000|
Salida<9>   |   11.864(R)|reloj_BUFGP       |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock reloj
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
reloj          |    3.129|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Thu Jan 15 16:30:18 2009
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Peak Memory Usage: 84 MB