crc_timesim.vhd

This Circuit generates the syndrome for the CRC. This is quite useful for transmision purposes and e

      O => E8_Dout_CLKINV
    );
  E5_Dout_DYMUX_15 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => E4_Dout,
      O => E5_Dout_DYMUX
    );
  E5_Dout_CLKINV_16 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reloj_BUFGP,
      O => E5_Dout_CLKINV
    );
  E10_Dout_DYMUX_17 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => E9_Dout,
      O => E10_Dout_DYMUX
    );
  E10_Dout_CLKINV_18 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reloj_BUFGP,
      O => E10_Dout_CLKINV
    );
  E9_Dout_DYMUX_19 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => E8_Dout,
      O => E9_Dout_DYMUX
    );
  E9_Dout_CLKINV_20 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reloj_BUFGP,
      O => E9_Dout_CLKINV
    );
  E6_Dout_DYMUX_21 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => E5_Dout,
      O => E6_Dout_DYMUX
    );
  E6_Dout_CLKINV_22 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reloj_BUFGP,
      O => E6_Dout_CLKINV
    );
  E11_Dout_DYMUX_23 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => E10_Dout,
      O => E11_Dout_DYMUX
    );
  E11_Dout_CLKINV_24 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reloj_BUFGP,
      O => E11_Dout_CLKINV
    );
  E7_Dout_DYMUX_25 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => E6_Dout,
      O => E7_Dout_DYMUX
    );
  E7_Dout_CLKINV_26 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reloj_BUFGP,
      O => E7_Dout_CLKINV
    );
  Mxor_c6_Result1 : X_LUT4
    generic map(
      INIT => X"9696"
    )
    port map (
      ADR0 => E3_Dout,
      ADR1 => Entrada_IBUF,
      ADR2 => E12_Dout,
      ADR3 => VCC,
      O => Mxor_c6_Result1_O
    );
  E12_Dout_27 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => E1_Dout_DYMUX,
      CE => VCC,
      CLK => E1_Dout_CLKINV,
      SET => GND,
      RST => E1_Dout_FFY_RST,
      O => E12_Dout
    );
  E1_Dout_FFY_RSTOR : X_OR2
    port map (
      I0 => E1_Dout_SRINV,
      I1 => GSR,
      O => E1_Dout_FFY_RST
    );
  Mxor_ref_Result1 : X_LUT4
    generic map(
      INIT => X"0FF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Entrada_IBUF,
      ADR3 => E12_Dout,
      O => Mxor_ref_Result1_O
    );
  E1_Dout_28 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => E1_Dout_DXMUX,
      CE => VCC,
      CLK => E1_Dout_CLKINV,
      SET => GND,
      RST => E1_Dout_FFX_RST,
      O => E1_Dout
    );
  E1_Dout_FFX_RSTOR : X_OR2
    port map (
      I0 => E1_Dout_SRINV,
      I1 => GSR,
      O => E1_Dout_FFX_RST
    );
  E9_Dout_29 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => E9_Dout_DYMUX,
      CE => VCC,
      CLK => E9_Dout_CLKINV,
      SET => GND,
      RST => E9_Dout_FFY_RST,
      O => E9_Dout
    );
  E9_Dout_FFY_RSTOR : X_OR2
    port map (
      I0 => E9_Dout_FFY_RSTAND,
      I1 => GSR,
      O => E9_Dout_FFY_RST
    );
  E9_Dout_FFY_RSTAND_30 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Rst_IBUF,
      O => E9_Dout_FFY_RSTAND
    );
  E6_Dout_31 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => E6_Dout_DYMUX,
      CE => VCC,
      CLK => E6_Dout_CLKINV,
      SET => GND,
      RST => E6_Dout_FFY_RST,
      O => E6_Dout
    );
  E6_Dout_FFY_RSTOR : X_OR2
    port map (
      I0 => E6_Dout_FFY_RSTAND,
      I1 => GSR,
      O => E6_Dout_FFY_RST
    );
  E6_Dout_FFY_RSTAND_32 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Rst_IBUF,
      O => E6_Dout_FFY_RSTAND
    );
  E11_Dout_33 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => E11_Dout_DYMUX,
      CE => VCC,
      CLK => E11_Dout_CLKINV,
      SET => GND,
      RST => E11_Dout_FFY_RST,
      O => E11_Dout
    );
  E11_Dout_FFY_RSTOR : X_OR2
    port map (
      I0 => E11_Dout_FFY_RSTAND,
      I1 => GSR,
      O => E11_Dout_FFY_RST
    );
  E11_Dout_FFY_RSTAND_34 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Rst_IBUF,
      O => E11_Dout_FFY_RSTAND
    );
  E7_Dout_35 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => E7_Dout_DYMUX,
      CE => VCC,
      CLK => E7_Dout_CLKINV,
      SET => GND,
      RST => E7_Dout_FFY_RST,
      O => E7_Dout
    );
  E7_Dout_FFY_RSTOR : X_OR2
    port map (
      I0 => E7_Dout_FFY_RSTAND,
      I1 => GSR,
      O => E7_Dout_FFY_RST
    );
  E7_Dout_FFY_RSTAND_36 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Rst_IBUF,
      O => E7_Dout_FFY_RSTAND
    );
  E2_Dout_37 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => E3_Dout_DYMUX,
      CE => VCC,
      CLK => E3_Dout_CLKINV,
      SET => GND,
      RST => E3_Dout_FFY_RST,
      O => E2_Dout
    );
  E3_Dout_FFY_RSTOR : X_OR2
    port map (
      I0 => E3_Dout_SRINV,
      I1 => GSR,
      O => E3_Dout_FFY_RST
    );
  Mxor_c4_Result1 : X_LUT4
    generic map(
      INIT => X"9696"
    )
    port map (
      ADR0 => E12_Dout,
      ADR1 => E2_Dout,
      ADR2 => Entrada_IBUF,
      ADR3 => VCC,
      O => Mxor_c4_Result1_O
    );
  E3_Dout_38 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => E3_Dout_DXMUX,
      CE => VCC,
      CLK => E3_Dout_CLKINV,
      SET => GND,
      RST => E3_Dout_FFX_RST,
      O => E3_Dout
    );
  E3_Dout_FFX_RSTOR : X_OR2
    port map (
      I0 => E3_Dout_SRINV,
      I1 => GSR,
      O => E3_Dout_FFX_RST
    );
  E4_Dout_39 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => E4_Dout_DYMUX,
      CE => VCC,
      CLK => E4_Dout_CLKINV,
      SET => GND,
      RST => E4_Dout_FFY_RST,
      O => E4_Dout
    );
  E4_Dout_FFY_RSTOR : X_OR2
    port map (
      I0 => E4_Dout_FFY_RSTAND,
      I1 => GSR,
      O => E4_Dout_FFY_RST
    );
  E4_Dout_FFY_RSTAND_40 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Rst_IBUF,
      O => E4_Dout_FFY_RSTAND
    );
  E8_Dout_41 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => E8_Dout_DYMUX,
      CE => VCC,
      CLK => E8_Dout_CLKINV,
      SET => GND,
      RST => E8_Dout_FFY_RST,
      O => E8_Dout
    );
  E8_Dout_FFY_RSTOR : X_OR2
    port map (
      I0 => E8_Dout_FFY_RSTAND,
      I1 => GSR,
      O => E8_Dout_FFY_RST
    );
  E8_Dout_FFY_RSTAND_42 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Rst_IBUF,
      O => E8_Dout_FFY_RSTAND
    );
  E5_Dout_43 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => E5_Dout_DYMUX,
      CE => VCC,
      CLK => E5_Dout_CLKINV,
      SET => GND,
      RST => E5_Dout_FFY_RST,
      O => E5_Dout
    );
  E5_Dout_FFY_RSTOR : X_OR2
    port map (
      I0 => E5_Dout_FFY_RSTAND,
      I1 => GSR,
      O => E5_Dout_FFY_RST
    );
  E5_Dout_FFY_RSTAND_44 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Rst_IBUF,
      O => E5_Dout_FFY_RSTAND
    );
  E10_Dout_45 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => E10_Dout_DYMUX,
      CE => VCC,
      CLK => E10_Dout_CLKINV,
      SET => GND,
      RST => E10_Dout_FFY_RST,
      O => E10_Dout
    );
  E10_Dout_FFY_RSTOR : X_OR2
    port map (
      I0 => E10_Dout_FFY_RSTAND,
      I1 => GSR,
      O => E10_Dout_FFY_RST
    );
  E10_Dout_FFY_RSTAND_46 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Rst_IBUF,
      O => E10_Dout_FFY_RSTAND
    );
  GLOBAL_LOGIC1_VCC : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  Salida_10_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => E11_Dout,
      O => Salida_10_O
    );
  Salida_11_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => E12_Dout,
      O => Salida_11_O
    );
  Salida_0_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => E1_Dout,
      O => Salida_0_O
    );
  Salida_1_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => E2_Dout,
      O => Salida_1_O
    );
  Salida_2_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => E3_Dout,
      O => Salida_2_O
    );
  Salida_3_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => E4_Dout,
      O => Salida_3_O
    );
  Salida_4_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => E5_Dout,
      O => Salida_4_O
    );
  Salida_5_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => E6_Dout,
      O => Salida_5_O
    );
  Salida_6_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => E7_Dout,
      O => Salida_6_O
    );
  Salida_7_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => E8_Dout,
      O => Salida_7_O
    );
  Salida_8_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => E9_Dout,
      O => Salida_8_O
    );
  Salida_9_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => E10_Dout,
      O => Salida_9_O
    );
  NlwBlock_crc_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlock_crc_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;