crc_timesim.vhd

This Circuit generates the syndrome for the CRC. This is quite useful for transmision purposes and e

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: H.38
--  \   \         Application: netgen
--  /   /         Filename: crc_timesim.vhd
-- /___/   /\     Timestamp: Sat Jan 10 18:24:29 2009
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command: -intstyle ise -s 4 -pcf crc.pcf -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim crc.ncd crc_timesim.vhd 
-- Device: 3s400ft256-4 (PRODUCTION 1.35 2005-01-22)
-- Design Name: crc
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Verification Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity crc is
  port (
    Rst : in STD_LOGIC := 'X'; 
    reloj : in STD_LOGIC := 'X'; 
    Entrada : in STD_LOGIC := 'X'; 
    Salida : out STD_LOGIC_VECTOR ( 11 downto 0 ) 
  );
end crc;

architecture Structure of crc is
  signal E11_Dout : STD_LOGIC; 
  signal E12_Dout : STD_LOGIC; 
  signal E1_Dout : STD_LOGIC; 
  signal E2_Dout : STD_LOGIC; 
  signal E3_Dout : STD_LOGIC; 
  signal E4_Dout : STD_LOGIC; 
  signal E5_Dout : STD_LOGIC; 
  signal E6_Dout : STD_LOGIC; 
  signal reloj_BUFGP_IBUFG : STD_LOGIC; 
  signal E7_Dout : STD_LOGIC; 
  signal E8_Dout : STD_LOGIC; 
  signal E9_Dout : STD_LOGIC; 
  signal E10_Dout : STD_LOGIC; 
  signal Rst_IBUF : STD_LOGIC; 
  signal Entrada_IBUF : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal reloj_BUFGP : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal Salida_10_ENABLE : STD_LOGIC; 
  signal Salida_10_O : STD_LOGIC; 
  signal Salida_11_ENABLE : STD_LOGIC; 
  signal Salida_11_O : STD_LOGIC; 
  signal Salida_0_ENABLE : STD_LOGIC; 
  signal Salida_0_O : STD_LOGIC; 
  signal Salida_1_ENABLE : STD_LOGIC; 
  signal Salida_1_O : STD_LOGIC; 
  signal Salida_2_ENABLE : STD_LOGIC; 
  signal Salida_2_O : STD_LOGIC; 
  signal Salida_3_ENABLE : STD_LOGIC; 
  signal Salida_3_O : STD_LOGIC; 
  signal Salida_4_ENABLE : STD_LOGIC; 
  signal Salida_4_O : STD_LOGIC; 
  signal Salida_5_ENABLE : STD_LOGIC; 
  signal Salida_5_O : STD_LOGIC; 
  signal reloj_INBUF : STD_LOGIC; 
  signal Salida_6_ENABLE : STD_LOGIC; 
  signal Salida_6_O : STD_LOGIC; 
  signal Salida_7_ENABLE : STD_LOGIC; 
  signal Salida_7_O : STD_LOGIC; 
  signal Salida_8_ENABLE : STD_LOGIC; 
  signal Salida_8_O : STD_LOGIC; 
  signal Salida_9_ENABLE : STD_LOGIC; 
  signal Salida_9_O : STD_LOGIC; 
  signal Rst_INBUF : STD_LOGIC; 
  signal Entrada_INBUF : STD_LOGIC; 
  signal reloj_BUFGP_BUFG_S_INVNOT : STD_LOGIC; 
  signal E1_Dout_DXMUX : STD_LOGIC; 
  signal Mxor_ref_Result1_O : STD_LOGIC; 
  signal E1_Dout_DYMUX : STD_LOGIC; 
  signal Mxor_c15_Result1_O : STD_LOGIC; 
  signal E1_Dout_SRINV : STD_LOGIC; 
  signal E1_Dout_CLKINV : STD_LOGIC; 
  signal E3_Dout_DXMUX : STD_LOGIC; 
  signal Mxor_c4_Result1_O : STD_LOGIC; 
  signal E3_Dout_DYMUX : STD_LOGIC; 
  signal Mxor_c2_Result1_O : STD_LOGIC; 
  signal E3_Dout_SRINV : STD_LOGIC; 
  signal E3_Dout_CLKINV : STD_LOGIC; 
  signal E4_Dout_DYMUX : STD_LOGIC; 
  signal Mxor_c6_Result1_O : STD_LOGIC; 
  signal E4_Dout_CLKINV : STD_LOGIC; 
  signal E8_Dout_DYMUX : STD_LOGIC; 
  signal E8_Dout_CLKINV : STD_LOGIC; 
  signal E5_Dout_DYMUX : STD_LOGIC; 
  signal E5_Dout_CLKINV : STD_LOGIC; 
  signal E10_Dout_DYMUX : STD_LOGIC; 
  signal E10_Dout_CLKINV : STD_LOGIC; 
  signal E9_Dout_DYMUX : STD_LOGIC; 
  signal E9_Dout_CLKINV : STD_LOGIC; 
  signal E6_Dout_DYMUX : STD_LOGIC; 
  signal E6_Dout_CLKINV : STD_LOGIC; 
  signal E11_Dout_DYMUX : STD_LOGIC; 
  signal E11_Dout_CLKINV : STD_LOGIC; 
  signal E7_Dout_DYMUX : STD_LOGIC; 
  signal E7_Dout_CLKINV : STD_LOGIC; 
  signal E1_Dout_FFY_RST : STD_LOGIC; 
  signal E1_Dout_FFX_RST : STD_LOGIC; 
  signal E9_Dout_FFY_RST : STD_LOGIC; 
  signal E9_Dout_FFY_RSTAND : STD_LOGIC; 
  signal E6_Dout_FFY_RST : STD_LOGIC; 
  signal E6_Dout_FFY_RSTAND : STD_LOGIC; 
  signal E11_Dout_FFY_RST : STD_LOGIC; 
  signal E11_Dout_FFY_RSTAND : STD_LOGIC; 
  signal E7_Dout_FFY_RST : STD_LOGIC; 
  signal E7_Dout_FFY_RSTAND : STD_LOGIC; 
  signal E3_Dout_FFY_RST : STD_LOGIC; 
  signal E3_Dout_FFX_RST : STD_LOGIC; 
  signal E4_Dout_FFY_RST : STD_LOGIC; 
  signal E4_Dout_FFY_RSTAND : STD_LOGIC; 
  signal E8_Dout_FFY_RST : STD_LOGIC; 
  signal E8_Dout_FFY_RSTAND : STD_LOGIC; 
  signal E5_Dout_FFY_RST : STD_LOGIC; 
  signal E5_Dout_FFY_RSTAND : STD_LOGIC; 
  signal E10_Dout_FFY_RST : STD_LOGIC; 
  signal E10_Dout_FFY_RSTAND : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
begin
  Salida_10_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Salida_10_O,
      CTL => Salida_10_ENABLE,
      O => Salida(10)
    );
  Salida_10_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => Salida_10_ENABLE
    );
  Salida_11_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Salida_11_O,
      CTL => Salida_11_ENABLE,
      O => Salida(11)
    );
  Salida_11_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => Salida_11_ENABLE
    );
  Salida_0_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Salida_0_O,
      CTL => Salida_0_ENABLE,
      O => Salida(0)
    );
  Salida_0_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => Salida_0_ENABLE
    );
  Salida_1_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Salida_1_O,
      CTL => Salida_1_ENABLE,
      O => Salida(1)
    );
  Salida_1_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => Salida_1_ENABLE
    );
  Salida_2_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Salida_2_O,
      CTL => Salida_2_ENABLE,
      O => Salida(2)
    );
  Salida_2_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => Salida_2_ENABLE
    );
  Salida_3_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Salida_3_O,
      CTL => Salida_3_ENABLE,
      O => Salida(3)
    );
  Salida_3_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => Salida_3_ENABLE
    );
  Salida_4_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Salida_4_O,
      CTL => Salida_4_ENABLE,
      O => Salida(4)
    );
  Salida_4_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => Salida_4_ENABLE
    );
  Salida_5_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Salida_5_O,
      CTL => Salida_5_ENABLE,
      O => Salida(5)
    );
  Salida_5_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => Salida_5_ENABLE
    );
  reloj_BUFGP_IBUFG_0 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reloj,
      O => reloj_INBUF
    );
  reloj_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reloj_INBUF,
      O => reloj_BUFGP_IBUFG
    );
  Salida_6_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Salida_6_O,
      CTL => Salida_6_ENABLE,
      O => Salida(6)
    );
  Salida_6_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => Salida_6_ENABLE
    );
  Salida_7_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Salida_7_O,
      CTL => Salida_7_ENABLE,
      O => Salida(7)
    );
  Salida_7_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => Salida_7_ENABLE
    );
  Salida_8_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Salida_8_O,
      CTL => Salida_8_ENABLE,
      O => Salida(8)
    );
  Salida_8_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => Salida_8_ENABLE
    );
  Salida_9_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Salida_9_O,
      CTL => Salida_9_ENABLE,
      O => Salida(9)
    );
  Salida_9_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => Salida_9_ENABLE
    );
  Rst_IBUF_1 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Rst,
      O => Rst_INBUF
    );
  Rst_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Rst_INBUF,
      O => Rst_IBUF
    );
  Entrada_IBUF_2 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Entrada,
      O => Entrada_INBUF
    );
  Entrada_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Entrada_INBUF,
      O => Entrada_IBUF
    );
  reloj_BUFGP_BUFG : X_BUFGMUX
    port map (
      I0 => reloj_BUFGP_IBUFG,
      I1 => GND,
      S => reloj_BUFGP_BUFG_S_INVNOT,
      O => reloj_BUFGP,
      GSR => GSR
    );
  reloj_BUFGP_BUFG_SINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => reloj_BUFGP_BUFG_S_INVNOT
    );
  E1_Dout_DXMUX_3 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Mxor_ref_Result1_O,
      O => E1_Dout_DXMUX
    );
  E1_Dout_DYMUX_4 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Mxor_c15_Result1_O,
      O => E1_Dout_DYMUX
    );
  E1_Dout_SRINV_5 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Rst_IBUF,
      O => E1_Dout_SRINV
    );
  E1_Dout_CLKINV_6 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reloj_BUFGP,
      O => E1_Dout_CLKINV
    );
  Mxor_c15_Result1 : X_LUT4
    generic map(
      INIT => X"C33C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Entrada_IBUF,
      ADR2 => E11_Dout,
      ADR3 => E12_Dout,
      O => Mxor_c15_Result1_O
    );
  E3_Dout_DXMUX_7 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Mxor_c4_Result1_O,
      O => E3_Dout_DXMUX
    );
  E3_Dout_DYMUX_8 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Mxor_c2_Result1_O,
      O => E3_Dout_DYMUX
    );
  E3_Dout_SRINV_9 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Rst_IBUF,
      O => E3_Dout_SRINV
    );
  E3_Dout_CLKINV_10 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reloj_BUFGP,
      O => E3_Dout_CLKINV
    );
  Mxor_c2_Result1 : X_LUT4
    generic map(
      INIT => X"A55A"
    )
    port map (
      ADR0 => E12_Dout,
      ADR1 => VCC,
      ADR2 => Entrada_IBUF,
      ADR3 => E1_Dout,
      O => Mxor_c2_Result1_O
    );
  E4_Dout_DYMUX_11 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Mxor_c6_Result1_O,
      O => E4_Dout_DYMUX
    );
  E4_Dout_CLKINV_12 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reloj_BUFGP,
      O => E4_Dout_CLKINV
    );
  E8_Dout_DYMUX_13 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => E7_Dout,
      O => E8_Dout_DYMUX
    );
  E8_Dout_CLKINV_14 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reloj_BUFGP,