prueba_vhd.tdo

This Circuit generates the syndrome for the CRC. This is quite useful for transmision purposes and e

## NOTE: Do not edit this file.
## Auto generated by Project Navigator for VHDL Post-PAR Simulation
##
vlib work
## Compile Post-PAR Model for Module crc
vcom -87 -explicit  crc_timesim.vhd
vcom -93 -explicit  Prueba.vhd
vsim -t 1ps -sdfmax /UUT=crc_timesim.sdf  -lib work prueba_vhd
do {prueba_vhd.udo}
view wave
add wave *
view structure
view signals
run 1000ns
## End