crc.par

This Circuit generates the syndrome for the CRC. This is quite useful for transmision purposes and e

Release 7.1i par H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Bull::  Sat Jan 10 19:51:17 2009

par -w -intstyle ise -ol high -t 1 -n 3 crc_map.ncd mppr_result.dir crc.pcf 


Constraints file: crc.pcf.
Loading device for application Rf_Device from file '3s400.nph' in environment
C:/Xilinx.
   "crc" is an NCD, version 3.1, device xc3s400, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  1 out of 8      12%
   Number of External IOBs            15 out of 173     8%
      Number of LOCed IOBs             0 out of 15      0%

   Number of Slices                   10 out of 3584    1%
      Number of SLICEMs                0 out of 1792    0%



Overall effort level (-ol):   High (set by user)
Placer effort level (-pl):    High (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    High (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:9896cd) REAL time: 3 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 3 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 5 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 5 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 5 secs 

Phase 6.8
.
.
.
.
Phase 6.8 (Checksum:993891) REAL time: 5 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 5 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 5 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 5 secs 

Writing design to file mppr_result.dir/H_H_1.ncd


Total REAL time to Placer completion: 5 secs 
Total CPU time to Placer completion: 4 secs 

Starting Router

Phase 1: 55 unrouted;       REAL time: 5 secs 

Phase 2: 44 unrouted;       REAL time: 5 secs 

Phase 3: 6 unrouted;       REAL time: 5 secs 

Phase 4: 6 unrouted; (41)      REAL time: 6 secs 

Phase 5: 6 unrouted; (0)      REAL time: 6 secs 

Phase 6: 0 unrouted; (0)      REAL time: 6 secs 

Phase 7: 0 unrouted; (0)      REAL time: 6 secs 


Total REAL time to Router completion: 6 secs 
Total CPU time to Router completion: 4 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|         reloj_BUFGP |      BUFGMUX3| No   |   10 |  0.019     |  1.033      |
+---------------------+--------------+------+------+------------+-------------+


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.455
   The MAXIMUM PIN DELAY IS:                               3.922
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.158

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
          14          27          11           2           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 4 secs 

Peak Memory Usage:  84 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0

Writing design to file mppr_result.dir/H_H_1.ncd



PAR done!