tipod.vhd

来自「This Circuit generates the syndrome for 」· VHDL 代码 · 共 26 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TipoD is
    Port ( Rset : in std_logic;
           Din : in std_logic;
           clk : in std_logic;
           Dout : out std_logic);
end TipoD;

architecture Behavioral of TipoD is

begin
	  
  PROCESS (clk, Rset)
	
	BEGIN
		IF (Rset = '1') THEN	
			Dout<= '0';
		ELSIF (clk'EVENT AND clk= '1') THEN
			Dout<= Din;
		END IF;
	END PROCESS;

end Behavioral;