crc7.v

crc7 calculation for SDIO mode

module crc7 (
		clk,
		reset_n,
		reset_s,
		go,
		done,
		byte_in,
		crc_in,
		crc_out
	);
	
input clk;
input reset_n;	
input reset_s;
input go;
output done;

input [7:0]		byte_in;
input [7:0]		crc_in;
output [7:0]	crc_out;

parameter 
	ST_IDLE		= 8'h00,
	ST_INIT		= 8'h01,
	ST_LP_E0		= 8'h02,
	ST_LP_E1		= 8'h03,
	ST_FINZ		= 8'h04,
	ST_DONE		= 8'h05;
	
reg [7:0] state, next;

always @(posedge clk or negedge rst_n)
	if (!reset_n || reset_s) state <= ST_IDLE;
	else state <= next;
	
always @(state or go or i)
	begin
	next = 'bx;
	case (state)
		ST_IDLE	:	if (go) 	next = ST_INIT;
							else  next = ST_IDLE;
							
		ST_INIT	:				next = ST_LP_E0;
		ST_LP_E0	:				next = ST_LP_E1;
		ST_LP_E1	:	if (i<8'h08)
									next = ST_LP_E0;
						else		next = ST_DONE;
						
		ST_DONE  : 	if (!go) next = ST_IDLE;	
							else  next = ST_DONE;
	endcase
	end

always @(posedge clk or negedge rst_n)
	if (!reset_n || reset_s)
	begin
		done_r <= 1'b1;
	end	else 
	case (next)
		ST_INIT	:	begin	
						crc <= crc_in;
						done_r <= 1'b0;
						b <= byte_in;
						i <= 8'h00;
						end;
		ST_LP_E0	:	crc <= (crc << 1);
		ST_LP_E1	:	begin
						i <= i + 8'h01;
						if((crc ^ b) & 8'h80)
							crc <= (crc ^ 8'h09);
						b <= (b << 1);
						end;
		ST_DONE  :	done_r <= 1'b1;
	endcase

assign crc_out  = (crc & 8'h7f);
assign done = done_r && !go;

endmodule