📄 bootarm.s
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DCD 0x80040008
;
WATCHDOG_RESTART_VALUE
DCD 0x1971
;
EMI_BASE_REG
DCD 0x80010000
;
;EMI_26MHZ_SETTING
; DCD 0x44004202
;patch emi golden 26M setting
IF :DEF:MT6217 :LOR: :DEF:MT6218B :LOR: :DEF:MT6219 :LOR: :DEF:MT6223 :LOR: :DEF:MT6223P :LOR: :DEF:MT6226 :LOR: :DEF:MT6226M :LOR: :DEF:MT6226D :LOR: :DEF:MT6227 :LOR: :DEF:MT6227D
EMI_26MHZ_SETTING
DCD 0x44004404
ELSE
EMI_26MHZ_SETTING
DCD 0x20404405
ENDIF ;patch end
IF REMAPPING
MTK_INITIALIZE_PTR
DCD MTK_Initialize
ENDIF
;
RAND_NUM_SEED_PTR
DCD rand_num_seed
;
ABN_RST_PTR
DCD Abnormal_info_Pool
DCD DUMMY_END ; dummy reference to ensure DUMMY_END won't be optimized
;
;
;/*************************************************************************/
;/* */
;/* FUNCTION */
;/* */
;/* INT_Initialize */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function sets up the global system stack variable and */
;/* transfers control to the target independent initialization */
;/* function INC_Initialize. Responsibilities of this function */
;/* include the following: */
;/* */
;/* - Setup necessary processor/system control registers */
;/* - Initialize the vector table */
;/* - Setup the system stack pointers */
;/* - Setup the timer interrupt */
;/* - Calculate the timer HISR stack and priority */
;/* - Calculate the first available memory address */
;/* - Transfer control to INC_Initialize to initialize all of */
;/* the system components. */
;/* */
;/* CALLS */
;/* */
;/* INC_Initialize Common initialization */
;/* */
;/* INPUTS */
;/* */
;/* None */
;/* */
;/* OUTPUTS */
;/* */
;/* None */
;/* */
;/* */
;/*************************************************************************/
;VOID INT_Initialize(void)
;{
ENTRY
EXPORT INT_Initialize
INT_Initialize
; /* Insure that the processor is in supervisor mode. */
MRS a1,CPSR ; Pickup current CPSR
BIC a1,a1,#MODE_MASK ; Clear the mode bits
ORR a1,a1,#SUP_MODE ; Set the supervisor mode bits
ORR a1,a1,#LOCKOUT ; Insure IRQ/FIQ interrupts are
; locked out
MSR CPSR_cxsf,a1 ; Setup the new CPSR
IF REMAPPING
IF (:LNOT: :DEF: __FOTA_ENABLE__)
LDR a4,EMI_BASE_REG
IF :DEF: MT6229 :LOR: :DEF: MT6228 :LOR: :DEF: MT6225 :LOR: :DEF: MT6230
LDR a1,[a4,#0x60] ; Skip if it is an abnormal reset
ELSE
LDR a1,[a4,#0x40]
ENDIF
AND a1,a1,#0x03 ; under remapped configuration
MOV a2,#FLASH_SRAM_REMAP
CMP a1,a2
BEQ MTK_LoadPC
LDR a1,EMI_26MHZ_SETTING ; Setting EMI for 13MHz MCU clock
STR a1,[a4] ; C2WS=1, C2RS=1, WST=2, RLT=2
STR a1,[a4,#0x08] ; 16 bits device
MOV a2,#BOOTROM_FLASH_REMAP ; Restore remapping on \CS0 and \CS1
IF :DEF: MT6229 :LOR: :DEF: MT6228 :LOR: :DEF: MT6225 :LOR: :DEF: MT6230
STRH a2,[a4,#0x60]
ELSE
STRH a2,[a4,#0x40]
ENDIF
ENDIF ;___FOTA_ENABLE
IF (:LNOT: :DEF: __FOTA_ENABLE__)
MOV a1,#0x00 ; Copy Exception Vector table to RAM
LDR a2,ROM_Base_Ptr ; before remapping
LDR a3,EXTSRAM_Base_Ptr
ORR a3,a2,a3
Copy_INT_Entry
CMP a2,a3
LDRLO a4,[a1], #4
STRLO a4,[a2], #4
BLO Copy_INT_Entry
LDR a1,EMI_BASE_REG ; Remapping on \CS0 and \CS1
MOV a2,#FLASH_SRAM_REMAP
IF :DEF: MT6229 :LOR: :DEF: MT6228 :LOR: :DEF: MT6225 :LOR: :DEF: MT6230
STRH a2,[a1,#0x60]
ELSE
STRH a2,[a1,#0x40]
ENDIF
NOP
NOP
NOP
NOP
NOP
NOP
ELSE
MOV a1,#0x00 ; Copy Exception Vector table to RAM
LDR a2,ROM_Base_Ptr ; before remapping
LDR a3,INT_Table_END_PTR
ORR a3,a2,a3
Copy_INT_Entry
CMP a2,a3
LDRLO a4,[a2], #4
STRLO a4,[a1], #4
BLO Copy_INT_Entry
ENDIF
MTK_LoadPC
LDR pc,MTK_INITIALIZE_PTR
MTK_Initialize
ENDIF
LDR a1,WATCHDOG_RESTART_REG ; Restart watchdog
LDR a2,WATCHDOG_RESTART_VALUE
STR a2,[a1]
; /* keep lr and sp for abnormal case */
LDR a1,ABN_RST_PTR
STR lr,[a1] ; Where abnormal reset from?
STR sp,[a1, #0x4]
LDR a1,BOOT_SYS_Stack_End
MOV sp,a1 ; Setup initial stack pointer
IF REMAPPING ;read id need configure the write timing if not remapping
NOP
ELSE
LDR a4,EMI_BASE_REG
LDR a1,EMI_26MHZ_SETTING ; Setting EMI for 13MHz MCU clock
STR a1,[a4] ; C2WS=1, C2RS=1, WST=2, RLT=2
ENDIF ; end emi setting
BL CopyCODEtoRam;jump to copy read id code
LDR PC,INTSRAM_ADDR;
FINISH_READID
;
IF __CHIP_VERSION_CHECK__
LDR a4,=INT_Version_Check
MOV lr, pc
BX a4
ENDIF
; /* Check if abnormal reset */
LDR a1,ABN_RST_PTR
BL INT_SystemReset_Check
BL SST_DTLB_Init
; /* BL to INT_Config() to configure EMI wait state after system stack is set up */
BL INT_Config
; /*
; * NoteXXX: Store the return value of INT_Config (i.e.,random number seed)
; * in r12 temporarily. Thus in the following program r12 should be
; * used before we store r12 back to rand_num_seed.
; */
MOV r12,a1
; /* Initialize regions */
BL INT_InitRegions ; in regioninit.s
IF :DEF:__ROMSA_SUPPORT__ ; ROMSA
BL InitRegions2 ; ROMSA
BL ROMSA_Init ; ROMSA
ENDIF ; ROMSA
BL GetmemoryInformation
; /* after INT_InitRegions, we can store the random number seed to rand_num_seed */
LDR a2,RAND_NUM_SEED_PTR
STR r12,[a2]
BL custom_setAdvEMI
BL CacheInit
MOV a1,#1 ; All vectors are assumed loaded
LDR a2, Loaded_Flag
STR a1,[a2,#0] ; Initialize loaded flag
IF KAL_ON_NUCLEUS
LDR a1,BOOT_SYS_Stack
LDR a4,System_Limit ; Setup initial stack limit
STR a1,[a4, #0] ; Save stack limit
ENDIF
LDR a4, System_Stack
STR sp,[a4, #0] ; Save stack pointer
LDR a3,BOOT_IRQ_Stack_End
MRS a1,CPSR ; Pickup current CPSR
BIC a1,a1,#MODE_MASK ; Clear the mode bits
ORR a1,a1,#IRQ_MODE ; Set the IRQ mode bits
MSR CPSR_cxsf,a1 ; Move to IRQ mode
MOV sp,a3 ; Setup IRQ stack pointer
LDR a3,BOOT_FIQ_Stack_End
MRS a1,CPSR ; Pickup current CPSR
BIC a1,a1,#MODE_MASK ; Clear the mode bits
ORR a1,a1,#FIQ_MODE ; Set the FIQ mode bits
MSR CPSR_cxsf,a1 ; Move to the FIQ mode
MOV sp,a3 ; Setup FIQ stack pointer
LDR a3,BOOT_ABT_Stack_End
MRS a1,CPSR ; Pickup current CPSR
BIC a1,a1,#MODE_MASK ; Clear the mode bits
ORR a1,a1,#ABORT_MODE ; Set the Abort mode bits
MSR CPSR_cxsf,a1 ; Move to the Abort mode
MOV sp,a3 ; Setup Abort stack pointer
LDR a3,BOOT_UND_Stack_End
MRS a1,CPSR ; Pickup current CPSR
BIC a1,a1,#MODE_MASK ; Clear the mode bits
ORR a1,a1,#UND_MODE ; Set the Undefine mode bits
MSR CPSR_cxsf,a1 ; Move to the Undefine mode
MOV sp,a3 ; Setup Undefine stack pointer
LDR a3,BOOT_SYS_Stack_End
MRS a1,CPSR ; Pickup current CPSR
BIC a1,a1,#MODE_MASK ; Clear the mode bits
ORR a1,a1,#SYS_MODE ; Set the Undefine mode bits
MSR CPSR_cxsf,a1 ; Move to the Undefine mode
MOV sp,a3 ; Setup Undefine stack pointer
MRS a1,CPSR ; Pickup current CPSR
BIC a1,a1,#MODE_MASK ; Clear mode bits
ORR a1,a1,#SUP_MODE ; Set the supervisor mode bits
MSR CPSR_cxsf,a1 ; All interrupt stacks are setup,
IF KAL_ON_NUCLEUS
LDR a4,HISR_Stack_Ptr
LDR a3,BOOT_TMD_Stack
STR a3,[a4, #0] ; Setup timer HISR stack pointer
LDR a2,BOOT_Timer_HISR_Stack_Size
LDR a4,HISR_Stack_Size
STR a2,[a4, #0] ; Setup timer HISR stack size
MOV a2,#TIMER_PRIORITY ; Pickup timer HISR priority (0-2)
LDR a4,HISR_Priority
STR a2,[a4, #0] ; Setup timer HISR priority
ENDIF
MOV a1, #0
IF KAL_ON_NUCLEUS
[ THUMB
LDR a4,=INC_Initialize ; to high-level initialization
BX a4
|
B INC_Initialize ; to high-level initialization
]
ELSE
[ THUMB
LDR a4,=_tx_initialize_kernel_enter ; to high-level initialization
BX a4
|
B _tx_initialize_kernel_enter ; to high-level initialization
]
ENDIF
;}
;void CopyCODEtoRam() copy code to internal ram
;{
CopyCODEtoRam
LDR a1,DMA_PWRCTRL_ADDR
LDR a2,DMA_PWRCTRL_MASK
STRH a2,[a1];power on DMA controller,and we choose saving flash id to dma register
LDR a1,READIDSTART_PTR
LDR a2,READIDEND_PTR
LDR a3,INTSRAM_ADDR
Startcopy ;copy code to ram
CMP a1,a2
LDRLOH a4,[a1],#2
STRLOH a4,[a3],#2
BLO Startcopy
MOV pc,lr
INTSRAM_ADDR
DCD 0x40000000;based on mt6225
READIDSTART_PTR
DCD ReadIDStart
READIDEND_PTR
DCD ReadIDEnd
DMA_PWRCTRL_ADDR
DCD 0X80000320 ;based on mt6225
DMA_PWRCTRL_MASK
DCD 0x01
;}
;void ReadIDStart()
;{
ReadIDStart ;send read id command
LDR a1,AMD_RESET_ADDR
LDR a2,AMD_RESET_DATA
STRH a2,[a1];reset flash flash_base[00]=0xf0
LDR a1,AMD_ENTER_CFI_ADDR
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